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Old 13th August 2012, 02:59 PM   #151
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Quote:
Originally Posted by smms73 View Post

Only today i realize that pcm1794 has 7.8ma peak to peak, i was thinking it was 7.8ma peak, so all prior result of harmonic distortion have been made at 15,6ma peak to peak, at 7,8ma p-p the distortion is smaler, this version i apresent today has:
I am sure this has perhaps been mentioned but the above isn't quite true either. The PCM1794s outputs sit at a current of -6.2mA when the analogue outputs are doing nothing. That +-7.8mA then swings about this point from -14mA up to 1.6mA. The final summing stage in the TI implementation handles this and cancels the common offset from the differential outputs.
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Old 13th August 2012, 03:35 PM   #152
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Originally Posted by 5th element View Post
I am sure this has perhaps been mentioned but the above isn't quite true either. The PCM1794s outputs sit at a current of -6.2mA when the analogue outputs are doing nothing. That +-7.8mA then swings about this point from -14mA up to 1.6mA. The final summing stage in the TI implementation handles this and cancels the common offset from the differential outputs.
So, it is actually max 15.6mA p-p across the two Iout pins? If I were to simulate this with a differential current source, I should set it to 15.6mA p-p? I find this confusing.
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Old 13th August 2012, 03:58 PM   #153
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Yes it is. Each pin can swing plus or minus 7.8mA about the central point of -6.2mA. So if the + output is maximally high it will be at +1.6mA and if the - output is maximally low, it will sit at -14mA for a total difference of 15.6mA between the two output pins.
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Old 13th August 2012, 04:15 PM   #154
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Hmm that's the way I've always assumed it worked, but thinking about it. The output with 2VRMS uses 750R feedback resistors in the I/V converter, these then feed into the differential/summing configured opamp which has a 560/270 divider before it.

2V RMS = 5.64 volts peak to peak.

For this to be on the output of the differential opamp it would need to receive 5.64/2 volts peak to peak on each input pin, so 2.82 volts peak to peak. But in this case there is a potential divider before hand which halves the signal at each pin, so you'd need to multiple 2.82 by 2 again, to get the voltage back up. This leaves you at each I/V stage needing to output 5.64 Vp-p for the total output to = 2VRMS.

5.64/750 = 7.52, which is close enough to 7.8mA. So it would seem my assumption was incorrect and I've talked to people at TI using +-7.8mA and no one has ever corrected me! It is indeed swinging +-7.8/2. This keeps the entire current at the outputs negative for the entire output swing, which probably makes some sort of sense as to how the DAC works, otherwise, why offset the output at all?
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Old 13th August 2012, 04:40 PM   #155
zinsula is offline zinsula  Switzerland
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This should make everything clear:
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Old 13th August 2012, 05:51 PM   #156
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ok, that's good. I assumed it was 7.8mA p-p across the Iout pins in my simulations.
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Old 13th August 2012, 06:12 PM   #157
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The PCM1794A current outputs can be confusing. There are four output pins, +L, -L, +R, -R. Each output pin sinks a quiescent bias current of -6.2mA to ground. To help clarify the polarity of this bias current, an passive resistor I/V, for example, would develop a positive bias voltage with respect to ground from this bias current.

The dynamic signal current swing from EACH output pin is 3.9mA peak single-ended. Therfore, the peak-peak signal current swing from EACH output pin is 7.8mA single-ended. The DIFFERENTIAL output signal net current change for a given channel then is 7.8mA peak, and 15.6mA peak-peak.
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Old 13th August 2012, 11:33 PM   #158
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Hi,

You can't compensate the DAC centre current by increasing the upper ccs current. The DACs current is taken by the lower ccs (it's a current sourcing DAC). This would imbalance the symmetry of the stage since the lower half of the input stage of the circuit runs at higher current levels. Also heat dissation might become a problem, especially if the PNPs were SMDs. Therefore I only suggest a dedicated current sink from the DAC output to the negative supply.
Compensating for the Input Offset Voltage at the bases of Q2/3 changes the Output offset voltage considerably as well. Vice versa changes the compensation of Output Offset the Input Offset slightly. Getting both compensated might become a bit delicate. Since One probabely wants to add a Buffer Stage anyway it might be best to compensate only for the Input Offset and AC couple to the Buffer.

jauu
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Old 14th August 2012, 05:50 AM   #159
zinsula is offline zinsula  Switzerland
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Quote:
Originally Posted by Calvin View Post
You can't compensate the DAC centre current by increasing the upper ccs current. [...]
In this case, i cannot agree with you.

I think it's perfectly possible to unbalance the two current sources by 6.2 mA. One ccs has to deliver 6.2mA more than the other one sinks, if the DAC will sink this amount. It's even more elegant than a separate ccs.
Important is that the emitter current of Q3 and Q6 (Post #150) is equal (as will the currents in the input transistors be).

Regarding dissipation, you should always run much higher currents in such I/V's than the current swing of the DAC is, in order to keep input resistance low and stable (impedance of emitter follower depends from current and base impedance*beta).
If you run into dissipation problems because of an imbalance of 6.2mA, you are already biasing way to low.
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Old 14th August 2012, 07:51 AM   #160
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Quote:
Originally Posted by Calvin View Post
Hi,

You can't compensate the DAC centre current by increasing the upper ccs current. The DACs current is taken by the lower ccs (it's a current sourcing DAC). This would imbalance the symmetry of the stage since the lower half of the input stage of the circuit runs at higher current levels. Also heat dissation might become a problem, especially if the PNPs were SMDs. Therefore I only suggest a dedicated current sink from the DAC output to the negative supply.
Compensating for the Input Offset Voltage at the bases of Q2/3 changes the Output offset voltage considerably as well. Vice versa changes the compensation of Output Offset the Input Offset slightly. Getting both compensated might become a bit delicate. Since One probabely wants to add a Buffer Stage anyway it might be best to compensate only for the Input Offset and AC couple to the Buffer.

jauu
Calvin
Yes, sorry my mistake. you have to increase the lower current source to null the output offset created by the current imbalance of dac.

There is no problem in imbalance the symetry of the input stage, as this only increase the 2 harmonic distortion, and as this distortion are in phase they will be cancelled by the diferential stage.

Adding another current source in the input as you suggest will increase complexity and noise .

In respect to dissipation i must agree with zinsula, and you can always use more input bjt in parallel, to decrease individual bjt dissipation.
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