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Old 2nd July 2012, 12:44 PM   #1
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Default Balanced, 8XOS, ASRC, AD1865 DAC

I am attempting to build a DAC with 8x oversampling, ASRC, and balanced AD1865 DAC's.

The setup is like this:

CS8414 (Decode SP/DIF convert to I2S) -> AD1896 (Reduce Jitter/Resample everything to 44.1KHz (fed with 11.2896MHz super clock)) -> SM5842 (Oversampling filter fed with super clock) -> flip-flop (resample with super clock) -> 2x AD1865 (one supplied with L data and inverted L data, to create balanced outputs). This setup makes sense to me, advice would be greatly appreciated. I don't know if the AD1896 will communicate with the SM5842 as the data sheets say different thing's (right justified = LSBJ)??? Is the Flip-flop necessary to reduce jitter or could it be replaced with a inverter to get the inverted data signals for the DAC's?

I created a PCB layout with clock on separate PCB. I am not a DAC/PCB expert so advise on the layout would be greatly appreciated.

http://www.dddac.de/files/SM5842.pdf
http://www.analog.com/static/importe...ets/AD1896.pdf
http://www.analog.com/static/importe...ets/AD1865.pdf
http://www.jitter.de/pdfextern/8413-4.pdf
http://www.fairchildsemi.com/ds/MM/MM74HC175.pdf
http://cds.linear.com/docs/Datasheet/1963fc.pdf
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Last edited by benproiii; 2nd July 2012 at 12:48 PM.
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Old 3rd July 2012, 12:41 PM   #2
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Yes, you need DFF. Otherwise the jitter will suffer badly.
- Replace the CS8414 to something better, WM? Then you'll need to care 'bout 3.3-5v CMOS translation.
- Your clock distribution is bad. Check transmission lines.
In general - impedance control, single active source for every IC input.
That means:
- no jumpers
- need clock buffers (buffers or inverters - from fast logic family, not AC)
- reflection-suppressing resistors are at transmitter side.
- solid ground plane under clock's traces
- coax from clock PCB to DAC pcb
ASRC... is doubtful.
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Old 3rd July 2012, 05:37 PM   #3
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So I should add buffers to the clock lines & extend the ground plane around the clock trace? Should I remove the flip flop and just use an inverter to get the out of phase data signals. As the output of the ad1896 should already have low jitter?
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Old 4th July 2012, 09:41 AM   #4
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>>So I should add buffers to the clock lines & extend the ground plane around the clock trace?
Yes.
You'll have to control the impedance of traces.
With thick boards this is less easy, as your ground plane is far away of your traces.
Use Saturn PCB calculator to calculate trace impedances. With 2-sided board you have 2 choices - classic stripline - a conductor over ground plane. And coplanar waveguide - a conductor on ground plane + tightly surrounded by ground planes.
Stripline is better controlled, but requires thin board or too wide trace.
Coplanar thing is less controllable, requires precise spacing between ground plane surrounding, and tightness of 7-8mil conductor to ground plane spacing.

>>Should I remove the flip flop and just use an inverter to get the out of phase data signals.
No, you need DFF (D flip flop). It's called "reclocking". And by using 74HC175 you get inverted data for free.

>>As the output of the ad1896 should already have low jitter?
Somewhat ok jitter. Then you throw it's output to DF (digital filter) - that adds some jitter.
You want to have the jitter as low as possible. Simplest way of doing this is to "reclock" - then you'll have the jitter of clock + traces + maybe a buffer + DFF.
The less is in between, the less jitter you'll have.

You have 2 ICs that require low jitter thing.
1. DACs.
2. ASRC.



Draw a clocking block-scheme of your circuit. Circle the important traces, take care of them.
The rest is less important.


Then you'll need to be aware of EMC (electromagnetic compartability).
Rules of thumb - keep digital traces short, keep solid ground plane under these traces (no cutouts, no crossing traces).
Throw a ferrite bead on every digital IC PSU: PSU trace > Ferrite bead (near the IC) > IC Vcc ping > capacitor to ground.
Make sure you have smooth, solid, short ground plane from the grounded capacitor pin to GND pin of IC.
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Old 4th July 2012, 10:56 AM   #5
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Thank you for your help. I will try to mod the pcb accordingly.
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Old 4th July 2012, 01:29 PM   #6
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Could you post a higher resolution schematic? I can barely read the current one. Perhaps, it's my eyes, but I can't see from where the master clock source for the AD1896 (MCLK_I) is generated.
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Last edited by Ken Newton; 4th July 2012 at 01:32 PM.
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Old 4th July 2012, 01:47 PM   #7
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From external source /connector/, "superclock" of some sort.
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Old 4th July 2012, 05:05 PM   #8
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heres a new circuit diagram (the analog psu rails is not shown)
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Old 4th July 2012, 11:09 PM   #9
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Quote:
Originally Posted by s3tup View Post
From external source /connector/, "superclock" of some sort.
Okay.

What is your plan for the analog stages?
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Last edited by Ken Newton; 4th July 2012 at 11:12 PM.
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Old 4th July 2012, 11:44 PM   #10
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I plan on using 4 pass d1 Iv stages with fet ccs's and pass b1 buffer.
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