Using 16.9344Mhz clk to reclock 11.2986Mhz
I'm in the planning stage of a DAC project. I hope to replace the DAC PCB of my CD player so I can tap into the I2S data, no need for a receiver that way.
However, the data stream from the servo is controlled by a Sony CXP401. It can only run at 16.9344Mhz.
I have my heart set on using 6 CS4334 DAC's as they are cheap and I can get them easily. This is my 1st DAC project so my main aim is make one that works and hopefully make it sound good too without spending too much cash.
Problem is in order to use the DAC's on chip de-empasis they have to be clocked at 11.2896Mhz.
I can use divide the former clock by 1.5 to get the later but it wont have a 50% duty cycle. Is a 50% duty cycle required on a master clock or does the DAC ony see the rising edge os the clock waveform???
I can use a 2nd clock easily but I would like some clever way to use the 16.9mhz clock to reclock the 11.2mhz clock but this means reclocking against a rising edge and then the 2nd falling edge of the faster clock. Any ideas??
Or does anyone know of any alternative DAC's I can get easily and cheaply???
Or how many CD's I'm I likely to own that have empasis anyway!!??
Any help welcome
Unless I am misunderstanding you, your MCLK from transport is 16.9344Mhz and BCK, LRCK, DATA are the usual integer fractions of this rate.
If this is the case then the only way to be able to use digital de-emphasis is to asyncronously reclock the (entire) bitstream (ASRC). You can't cobble together some logic and change MCLK without changing the rest of the data associated with it!
One option in this case is to do the deemphasis in the analog realm.
And no, there aren't many CDs that have deemphasis.
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