Hi, i have SM5842 and 2xPCM58P-K.
View image: 100 4890
I wan to make SPDIF DAC with them, and for SPDIF receiver i think to use WM8804. But i am not sure how to connect WM8804 with SM5842. SM5842 support Left Justified input format. But WM8804 output format is "Left Justified with flags". What mean this "flags", and is this format will work proper? I'll appreciate any help to solve that problem.
View image: 100 4890
I wan to make SPDIF DAC with them, and for SPDIF receiver i think to use WM8804. But i am not sure how to connect WM8804 with SM5842. SM5842 support Left Justified input format. But WM8804 output format is "Left Justified with flags". What mean this "flags", and is this format will work proper? I'll appreciate any help to solve that problem.
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SM supports LJ and RJ, check page 17 of http://www.dddac.de/files/SM5842.pdf
It has "TTL compatible" inputs/outputs, but their trip voltage is somehow high at 2.5v. WM may work here.
The "flags" thing shouldn't puzzle you, as SM will ignore everything that comes after LSB.
It has "TTL compatible" inputs/outputs, but their trip voltage is somehow high at 2.5v. WM may work here.
The "flags" thing shouldn't puzzle you, as SM will ignore everything that comes after LSB.
Now I look the page 3 http://www.dddac.de/files/SM5842.pdf. If I understand correct, to accept left justified format I must have to make INF1N – HIGH and DI/INF2N – LOW, the input data being now IW1N/DIL and IW2N/DIR. Is it right this pin configuration? I am not sure is it Left Justified format=LR alternating, leading data?
You are right,
Page 17, fig. 5 on SM's DS shows us the signal timings.
The data is close to the left, and comes simultaneously with LRCLK = LJ.
I2S format would be the same, but with data channel delayed by 1bclk after the lrclk change.
WM's datasheet shows the same timings at page 48, fig. 23.
http://www.qobuz.com/info/IMG/pdf/wm8804.pdf
It appears the SM needs it's DIR/DIL pins connected together to properly load channel interleaved LJ, as it takes L_CH from DIL and R_CH from DIR.
Page 17, fig. 5 on SM's DS shows us the signal timings.
The data is close to the left, and comes simultaneously with LRCLK = LJ.
I2S format would be the same, but with data channel delayed by 1bclk after the lrclk change.
WM's datasheet shows the same timings at page 48, fig. 23.
http://www.qobuz.com/info/IMG/pdf/wm8804.pdf
It appears the SM needs it's DIR/DIL pins connected together to properly load channel interleaved LJ, as it takes L_CH from DIL and R_CH from DIR.
Thank you for explanation. I made the schematic, and configure the SM5842. Can you take a look, for errors in my schematic.
I'm little confused. On page 3, the table of pin 4. "LR alternating, leading data" is configured with INF1N-HIGH and DI/INF2N-LOW. But the figure5 on page 17 says that INF1N=INF2N=HIGH?
http://postimage.org/image/xe9togext/
I'm little confused. On page 3, the table of pin 4. "LR alternating, leading data" is configured with INF1N-HIGH and DI/INF2N-LOW. But the figure5 on page 17 says that INF1N=INF2N=HIGH?
http://postimage.org/image/xe9togext/
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