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|7th June 2012, 12:16 AM||#1|
Join Date: Jan 2004
DIT4096 and CS8406 hardware mode audio formats
For years I'd have trouble understanding what was going on with the audio formats supported in the DIT4096 and CS8406 ICs in hardware mode. Both chips seem to be identical in terms of functionality. The audio format is set by two pins on both ICs, incidentally the same way. They both support 24 bit left justified, I2S, 24 bit right justified, and 16 bit right justified. My question is, how does one determine what an audio source will output, and what does it mean?
For the DIT4096, I've seen two schematics on this site for modifications of Sony CD players. In both schematics the DIT4096 was configured for 16 bit right justified. Is 16 bit right justified common for CD players?
On the internet I've seen schematics using the CS8406 in video game consoles for adding S/PDIF output. In the modifications for Sega Saturn, Sega Dreamcast, and SNES, the CS8406 has been configured for 16 bit right justified. So does this mean it's common for those videogame consoles to use the 16 bit right justified format?
For the Nintendo Gamecube, PSX, SNES, and Sega Saturn, the TC9231N was also used in earlier designs, but the word clock was always inverted with a logic IC. The TC9231N only seems to support EIA-J and no other formats. So this would mean that those consoles also output in 16 bit right justified, except if you are using an EIA-J IC like the TC9231N, the word clock must be inverted.
And another thing I've noticed with XM radios using the older decoder ICs, specifically the STA450, always seem to output data in I2S with a 24 bit sample length. The register description in the datasheet for configuration of the output format on the STA450 says:
HOST_Pcmcnf Address : 0x4F Type : R/W Software Reset : NA Hardware Reset : NA Description This register is red by STA450A before to leave the wait mode. Pcm_prec Bit [1:0] 00: 16 bits mode. 01: 18 bits mode 10: 20 bits mode 11: 24 bits mode Invert_sclk Bit 2 0: LRCLK and PCM_OUT sampled on the falling edge of the SCLK 1: LRCLK and PCM_OUT sampled on the raising edge of the SCLK Format Bit 3 0: the output is in I2S format. 1: the output is in SONY format. Invert_lrclk Bit 4 0: LRCLK = 0 (low) will select the left channel. 1: LRCLK = 1 (high) will select the left channel Pcm_dif Bit 5 0: data are in the last SCLK cycles of LRCLK (right aligned) 1: data are in the first SCLK cycles of LRCLK (left aligned) Pcm_ord Bit 6 0: the transmission is done LSB first. 1: the transmission is done MSB first. Pcm_iec_chansel Bit 7 0: no iec958 output. 1: iec958 output, data on I2S pin (PCSD) are no more valid.
But, it seems like the register is always configured for I2S and 24 bit sample length. This is the case on a lot of the earlier radio's I've looked at. There were two DIT4096 schematics floating around the net at the time when I was experimenting with these radios, and both of them had the DIT4096 configured for I2S.
Another thing you may notice is the mention of IEC958 output. The STA450 had a pin which directly outputted TTL S/PDIF. It was turned on and off by a register, but in the radio's I've experimented with, it was always enabled, even the car radio tuners. I've used this output quite often and it worked very well with whatever driver interface I've decided to use. One thing that always puzzled me to this day is that the only XM radio that had S/PDIF output never utilized it, it used an S/PDIF interface IC.
With all that, that leaves me with one last question. Does the I2S standard specifically state a specific sample length, or can any sample length be used? And also, why do these S/PDIF interface ICs need to know the format? I would guess so the IC knows where to put the data and how to multiplex all of the clocks together.
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