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Old 9th October 2003, 01:13 PM   #1
mlloyd1 is offline mlloyd1  United States
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Default clock regeneration article on

Worry about clocks,jitter, etc.?, Maybe some interesting reading here
"Programmable clock regeneration techniques get signals through extreme conditions"

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Old 11th October 2003, 12:11 AM   #2
andrei is offline andrei  Canada
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Interesting. Using one of these "failsafe" clock buffers (CY23FS04/CY23FS08) will significantly clean up DIR-recovered clock at very small expense in money/board space. Very interesting indeed...
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Old 12th October 2003, 08:22 AM   #3
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Smile Clock Distribution Article

Hi Michael,
Interesting article, but not for the novice.
Andrei, I did not find the CY23FS06 and CY23FS08 in the article but here:
I will dig into it.
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Old 12th October 2003, 11:00 PM   #4
andrei is offline andrei  Canada
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The CY23FS04/CY23FS08 datasheets are at the Cypress website. Take a special look at the application note "Using Failsafe CY23FS08 as a Clock Jitter Reducton Device". The only external component required is a standard crystal (which is cheap and easily available in digital audio clock frequencies, unlike VCXO modules). Plus you get 3/7 buffered clock outputs for free, which you probably need anyway unless you are using monolythic digital filter/DAC chip.

To repeat myself, very interesting...
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