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Old 25th April 2012, 05:30 PM   #1
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Question How to calculate fs bit clock knowing crystal frequency?

How to calculate fs bit clock knowing crystal frequency?
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Old 25th April 2012, 06:21 PM   #2
TheGimp is offline TheGimp  United States
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According to the data sheet for the WM8741, the crystal frequency is fs.

fs/divide ratio (32, 64, 128, 256, etc) gives the data rate.

eg. 24.576ZMHz clock /256(divide ratio) = 192KHz data rate.

I suspect it is dependent on the DAC.

What device are you using?
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Old 25th April 2012, 07:17 PM   #3
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My device have a clock of 16.9344MHz, wich fs have?
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Old 25th April 2012, 08:16 PM   #4
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The bitclock (BCLK) frequency can be calculated as follows below.

1. If the left and right channel data are in multiplexed serial format (such as they typically are before entering an oversampling interpolator) then: BLCK = original input sample rate (Fs) * the oversampling ratio * 64 bits per frame.

2. If the left and right channel data are in de-multiplexed parallel format (such as they typically are after exiting an oversampling interpolator), then: BCLK = the original input sample rate (Fs) * the oversampling ratio * 32 bits per frame.

For points in the DAC where oversampling has not been applied, the oversampling ratio in the above formulas = 1.

Note: There also is a rarely utilized de-multiplexed parallel 16 bits per frame I2S data format.
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Last edited by Ken Newton; 25th April 2012 at 08:29 PM.
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Old 25th April 2012, 09:33 PM   #5
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Still don't know how to calculate?
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Old 27th April 2012, 03:57 PM   #6
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Anybody can help me?
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Old 27th April 2012, 04:04 PM   #7
TheGimp is offline TheGimp  United States
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What is your crystal frequency?

What DAC or part are you using?

What sample frequency (44.1K, 48K, etc)?
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Old 27th April 2012, 04:08 PM   #8
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Quote:
Originally Posted by TheGimp View Post
What is your crystal frequency?

What DAC or part are you using?

What sample frequency (44.1K, 48K, etc)?
Transport CEC TL1 crystal frequency 16.9344 MHz

DAC TP Buffalo III

Transport CEC TL1 uses CD red book 44.1KHz

Last edited by merlin el mago; 27th April 2012 at 04:16 PM.
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Old 27th April 2012, 04:16 PM   #9
kevinkr is offline kevinkr  United States
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How are you connecting the dac to the transport I2S (presumably) or spdif? I think you need to provide some information on the transport chip set as well.
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Old 27th April 2012, 04:20 PM   #10
glt is offline glt  United States
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It is implementation dependent. You could guess that it is 256fs

44.1x256=11.2896MHz
11.2896*3=33.8688MHz
33.8688MHz/2=16.9344MHz

In this case the clock goes through some logic to be multiplied by 2 and then divided by 3 to arrive at 256fs.

So it depends what kind of multiplication and division the clock goes through
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