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Old 7th September 2012, 08:17 AM   #51
qusp is offline qusp  Australia
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indeed rev 2 looks perfect for my purposes, except for the power consumption, as I want to make a trans-portable digital audio player to use with my portable ESS dac/balanced headphone amp.
I think its unlikely it will do 384khz
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Old 7th September 2012, 08:52 AM   #52
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Quote:
Originally Posted by qusp View Post
I think its unlikely it will do 384khz
I wouldn't be so sure ...
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Old 7th September 2012, 08:56 AM   #53
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happy to be proved wrong there, it just seems unlikely given its still a shared port and if its pulling it in over wifi, processing then passing it out again, or the i2s goes out over another connection? I thought it was P5 as well? I was thinking more, like most problems with these things so far, that it would be a bus and/or driver bottleneck that would prevent it, not the CPU
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Old 7th September 2012, 02:04 PM   #54
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384kHz = 384k*6=2.3MB/sec
I think it will work, for USB HDD or SSD read.

RPi PCM/I2S has Interrupt, DMA, TX FIFO.
large buffer, ex, 512KB + 512KB buffer will give 250msec cycle for audio playback application.
So I think it's possible, at least without driver, fully in application.
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Old 7th September 2012, 02:22 PM   #55
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Quote:
Originally Posted by KOON3876 View Post
384kHz = 384k*6=2.3MB/sec
I think it will work, for USB HDD or SSD read.

RPi PCM/I2S has Interrupt, DMA, TX FIFO.
large buffer, ex, 512KB + 512KB buffer will give 250msec cycle for audio playback application.
So I think it's possible, at least without driver, fully in application.
Sounds promising. I calculated a needed data rate of (384*64)/8=3.072MB/sec. Let's see what the real thing will be up for.
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Old 8th September 2012, 05:35 AM   #56
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Hi vzs, 3.072MB/sec is PCM output data rate (32bit x 2)
384k/24bit wav file read rate, and on memory copy = 384k * 24bit / 8bit * 2ch = 2.3MB/sec.
This rate is required to read out wav file, it should be no problem when there are no other large transaction on USB.
I tested 100 x 1MB memcpy() on raspberry Pi, and result was 263MB/sec so memory bandwidth has no problem at all.

from BCM2385 ARM peripherals.pdf, so far I don't see any reason we can not use Raspberry Pi as a bit-perfect I2S player.
"It supports many classic PCM formats including I2S" "The length and polarity of the frame sync is fully programmable and it can be used as a standard frame sync signal, or as an L-R signal for I2S."
=> I2S OK

"Each channel can be between 8 and 32 bits wide"
=> up to 32bit

"The direction of the PCM_CLK and PCM_FS signals can be individually selected" "In clock slave mode (CLKM=1), the PCM_CLK is an input, supplied by some external clock source."
=> we can use external pure 11.2896MHz xtal, no PLL

"PCM Clock Disable: 1 = Disable the PCM Clock. This cleanly disables the PCM clock. This enables glitch free clock switching between an internal and an uncontrollable external clock. The PCM clock can be disabled, and then the clock source switched, and then the clock re- enabled."
=> ready for external clock selection(44.1k / 192k etc), with GPIO and external selector logic.

"CH1POS : Channel 1 Position. This sets the bit clock at which the first bit (MS bit) of channel 1 data occurs in the frame. 0 indicates the first clock of frame."
=> set this to 0x01 for I2S format
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Old 8th September 2012, 06:07 AM   #57
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FYI, tested with Lexar JumpDrive USB stick. it was mounted as /dev/sda1
enough for high res file.

$ sudo apt-get install hdparm
:
$ sudo hdparm -fTt /dev/sda1
/dev/sda1:
Timing cached reads: 284 MB in 2.01 seconds = 141.49 MB/sec
Timing buffered disk reads: 44 MB in 3.02 seconds = 14.57 MB/sec
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Old 10th September 2012, 08:25 AM   #58
vzs is offline vzs  Europe
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Quote:
Originally Posted by KOON3876 View Post
3.072MB/sec is PCM output data rate (32bit x 2)
384k/24bit wav file read rate, and on memory copy = 384k * 24bit / 8bit * 2ch = 2.3MB/sec.

...from BCM2385 ARM peripherals.pdf, so far I don't see any reason we can not use Raspberry Pi as a bit-perfect I2S player.
"It supports many classic PCM formats including I2S" "The length and polarity of the frame sync is fully programmable and it can be used as a standard frame sync signal, or as an L-R signal for I2S."
=> I2S OK

"Each channel can be between 8 and 32 bits wide"
=> up to 32bit

"The direction of the PCM_CLK and PCM_FS signals can be individually selected" "In clock slave mode (CLKM=1), the PCM_CLK is an input, supplied by some external clock source."
=> we can use external pure 11.2896MHz xtal, no PLL

"PCM Clock Disable: 1 = Disable the PCM Clock. This cleanly disables the PCM clock. This enables glitch free clock switching between an internal and an uncontrollable external clock. The PCM clock can be disabled, and then the clock source switched, and then the clock re- enabled."
=> ready for external clock selection(44.1k / 192k etc), with GPIO and external selector logic.

"CH1POS : Channel 1 Position. This sets the bit clock at which the first bit (MS bit) of channel 1 data occurs in the frame. 0 indicates the first clock of frame."
=> set this to 0x01 for I2S format
My calculation was wrong indeed.

The datasheet of BCM2385 doesn't say anything about the speed capabilities of the PCM interface. To support 352.8/384KHz the PCM should be capable to handle PCM_CLK of 24.576MHz. This would be nice to check before building an external interface board.

I don't quite understand how the external clock selection should work. What tells the external clock selector module what PCM clock speed to provide?
I'm thinking about a clock selector board that has two clocks 22.5792Mhz and 24.576Mhz, a clock divider with 74VHC393 and PCM clock speeds selectable for /1 /2 /4 /8 (through a BCD to decimal and some AND gates).
For this to work the RPi should specify the division factor and the frequency domain used 44.1k or 48k multiplies.
Am I thinking right or how can this be done in another way?

Thanks. Zsolt
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Old 10th September 2012, 09:41 AM   #59
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...Further chewing upon the external clock board I came to conclusion that having Ian's FIFO I don't need an external clock board at all and will be OK with the jittery PLL clock generated by the RPi - provided that is not too jittery to over/under flow the FIFO.
Of course an external clock selection board plus some re-clocking would make the FIFO redundant but since it's here on my desk I would only need to hook it to the RPi.
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Old 10th September 2012, 11:14 AM   #60
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for me it would need to be able to handle 90.3168/98.304MHz, while leaving the ESS OSF enabled. unless I use some sort of multiplier.

I think even with fifo we need to make sure its an audio frequency clock rate, the fifo will do what it can, but cant reverse aliasing
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