DSD Playback system, DSF Player + USB DDC + DSD Amplifier

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I have some DSD music file from SACD now. I want to listen to them as it is.
So I made prototype of full DSD playback system.

(1) DSD File player (source, DSF hex dump screenshot)
Read DSF format DSD file into memory, make byte(= 8ch) stream, send to USB DSD digital-digital converter.
Now 1 Byte data contains 2 bit (L,R) only, but for future I want to playback 5.1 DSD. so I use 1 byte for 2 bit sample.

(2) DSD DDC (Photo, Schematic, VHDL) Right side of the photo
This is FTDI UM232H + FIFO + FPGA, to make +- output to DSD amplifier.
Made for USB - I2S x 24ch (see "Digital Line" forum).
FPGA is too large for DSD.. only 27 FFs are used.

These (1) (2) are just making bit stream to the (3).

(3) DSD amplifier (Photo, Schematic, Signal Photo) Left side of the photo
MOSFET Driver + MOSFET, 1bit amplifier. just a High Speed H bridge and LPF.
Volume is controlled by Final stage voltage. (0.0 - 6V)
Note: I'm using LOW side driver so Final stage voltage is limited, driver - 5V.
If you use High/Low side driver, you can apply any power.

It sounds. :)
Byte stream, which contains DSD signal, and H bridge + LPF can playback the Audio (as DSD theory is)
I have no experience with SHARP 1 Bit amplifier. This one sounds like SHARP? I hope so.
 

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Hi Sonic
You mean Dead-time control? Yes I selected the driver without timing control.
I loss some power (10ns/300ns or so) / I get correct pulse width.
dead time control reduces on-width of pulse = distortion.
same as analog amp, we need some power loss = idle current for quality.

This is prototype so I want to know which driver is the best, or thinking to design adequate driver circuit (for audio) by myself.
 
IMO with MOS like IRF you get less distortion with a small dead-time. You won't get anyway a "clean" transition there, it's still at zero, being a short-circuit between rails. Reduced voltage dip on rails at zero crossing and lower temperature on finals will help lowering the distortions.
How small can that time be... is up to how fast are those finals.
Sorry, ideea is good, but I found out long time ago that the final stage needs to be analogic. At least this is the state of electronic devices in this decade. 0.2% is nothing to care. Add one more zero and we are talking replacing the analog final stage.
 
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Sonic,
That is just a difference of our tastes, I want to "reduce".. the DAC chip, I/V, opamp, volume, JFET input, NFB, driver stage and Final stage and emitter register. and multiple toroidal and huge capacitors..
less analog is better for me.

for another idea,
https://sites.google.com/site/koonaudioprojects/power-dac
I once made Power DAC (PCM to current, to drive speaker) before.
It was PCM so bit accuracy was weak point, but by DSD I just need 1 current source / 1 current sink, big enough to drive speaker.
Which one do you think better for audio?
switching voltage by DSD, or current push / pull by DSD?
 
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That is just a difference of our tastes

It is an endless topic to discuss since taste of sound is different to human ears. For hobbyist, I recommend to go ahead your preference and regardless any diyers with opposite commend. For commercial interest, you build audio gears as per customer’s comment on taste of sound and independent of your taste of sound. For this reason, you shall feel happy if select your preference in hobbyist or make profit in commercial interest. It is the end of my philosophy for DIY sharing.
 
Nobody "commends" him what to do.
This is a forum and the purpose of it is the discussion, sharing ideeas and experiences. Blogs are more appropiate for talking to yourself.

Back to forum mode:
I think that if you don't have a feedback loop, and stay purelly digital, you need voltage switching. Curent sources are analogic only in my experience.
 
Sorry I'm just scribbling what I'm interested / I made:eek:

Dead_Time control, should be something like attached?
drive signal = function(input, input_delay1, input_delay2)
(1) High drive signal should have same length, as pulse width
(2) Low drive signal has narrow on time than High
(3) each signal should pass through same number of logic gate

Voltage_switching: now looking signals, with modified R-C and Schottky diode between D-S. I hate switching noise:(
1 bit Current Push-pull, if I try: switching was very smooth, I remember. with my understanding, this is not analogic because.. each FET does not know "analog signal voltage" itself. FET/driver only knows current bit 1/0.
NFB: there are no feedback for signal, (to add, I need 1 bit A/D) so Power supply must have feedback.
 

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PCM to DSD conversion?

Now I want to understand DSD,
I made x64 upsampler, so now I get 2.822MHz float PCM.
(Image, Right, shows 1kHz sign wave - 64 upsampled - 22.5k FIR LPFed)

next I need to apply 7th order noise shaper.
I could design H(z) = A(z)/B(z) as attached image (left).
here is Scilab command.

z=%z;
H=(1-6.996482471749818*z^(-1)+20.982415870011799*z^(-2)-34.964835250398139*z^(-3)+34.964835250398139*z^(-4)-20.982415870011799*z^(-5)+6.996482471749818*z^(-6)-1.000000000000000*z^(-7));
D=(1-5.250000000000000*z^(-1)+11.812500000000000*z^(-2)-14.765625000000000*z^(-3)+11.074218750000000*z^(-4)-4.983398437500000*z^(-5)+1.245849609375000*z^(-6)-0.133483886718750*z^(-7));
sys=syslin("d",H/D);
clf();
f1=scf(0);
plzr(sys)
f1=scf(1);
gainplot(sys,1e-3,1e-1,0.001)

Now I'm wondering how to program this H as IIR filter.
anyone know how to program IIR in DSP? :confused:
 

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Attachment, white noise maker:confused:
sorry, I'm trying to convert PCM to DSD.

(1) read wave file to memory
(2) prepare DSD header
(3) prepare FIR filter
(4) prepare Shaper parameter NG?
Loop
(5) oversample x64
(6) apply FIR LPF
(7) apply 7th noise shaper IIR NG?
(8) pack to DSD, write to file
Loopend

If this program run, I can convert PCM to DSD anytime.
(realtime, in the ASIO driver, or convert wav to DSD through x64 float upsampling)
 

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For DSD programming - maybe you can talk to kode54?
For dead time - now you are showing a bridge...
Anyway, the timings for B side can be the same like the ones on the A side, no need for extra delay there (you have the load between A and B, it won't "short" the supply).
Analog timings are instable, you would have to give a big safety margin. I would delay them in software.
 
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I was told some parameter and how to implement 7th order noise shaper on the book, and it is working. But still I can not understand how these parameters were calculated :eek:

Green dot: oversampled (0 inserted) 1kHz signal
Red line: 22k LPF passed, this is 2.8MHz sampling rate signal
Then (not on the graph, DSD signal = +1/-1)
Blue line: DSD signal passed LPF again. 1kHz signal reproduced. you can see FIR is starting around 1000 sample point.

10 seconds of WAV file is converted to DSD within around 5 seconds.

I will keep studying, but so far, I can produce DSD stream in realtime from PCM. it means I can modify my ASIO driver to produce DSD stream, to my 1bit amp. interesting:) I don't need any DAC chip, TI's amp, only need DSD byte stream and FET driver.
 

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