Thinking about inverting the I2S signal and producing L+/L- and R+/R- for balanced DAC operation.
I am trying to understand where the alleged 1-bit shift is coming when a simple inverter is used, instead of the more difficult 32-bit shift register solution described elsewhere. Obviously the L+ and L- can not be handled by the same chip with the simple inverter.
The issue is I don't see any 1-bit shift with the simple inverter, others are referring to. Let's take the offset binary range 0000 to FFFF. The 2s complement will be 8000 to 7FFF, the zero is 0000, -1 is represented by FFFF, +1 is represented by 0001. Now, inverting the binary signal and adding it to the original results 0000 (overflow truncated). I don't see any 1-bit shift.
Here is another thing that confuses me: let's take the analog signal. Any positive value between 0 and +LSB converts to 0000. Any negative value between 0 and -LSB converts to -1 (FFFF in 2s complement representation). So a small noise superposed on zero will cause alternating between 0000 and FFFF. This is because there is no round-up, just truncation. Does it mean the "real" analog zero is at -1/2, i.e. halfway between 0 and -1?
Should we worry about this at all, or is it just pure perfectionism?
I am trying to understand where the alleged 1-bit shift is coming when a simple inverter is used, instead of the more difficult 32-bit shift register solution described elsewhere. Obviously the L+ and L- can not be handled by the same chip with the simple inverter.
The issue is I don't see any 1-bit shift with the simple inverter, others are referring to. Let's take the offset binary range 0000 to FFFF. The 2s complement will be 8000 to 7FFF, the zero is 0000, -1 is represented by FFFF, +1 is represented by 0001. Now, inverting the binary signal and adding it to the original results 0000 (overflow truncated). I don't see any 1-bit shift.
Here is another thing that confuses me: let's take the analog signal. Any positive value between 0 and +LSB converts to 0000. Any negative value between 0 and -LSB converts to -1 (FFFF in 2s complement representation). So a small noise superposed on zero will cause alternating between 0000 and FFFF. This is because there is no round-up, just truncation. Does it mean the "real" analog zero is at -1/2, i.e. halfway between 0 and -1?
Should we worry about this at all, or is it just pure perfectionism?
Using an inverter gives the 1's complement. Audio data is in 2's complement. The difference between the two is 1LSB. I myself don't consider such a small difference a problem, but its a real difference, not an imagined one. If you want the signal perfectly inverted you'll need to add 1LSB to the 1's complement.
I have been listening to my dual 1541a dac with one dac receiving inverted data for 2 weeks and cannot hear anything unwanted. Its only the lsb that is in error - my argument for ignoring this is: -
When playing a track, there is always some background noise present from the recording environment (no recordings are done in anechoic chambers) and the chain from mic, ADCs, mixing desk, to recorder and this noise will mask (dither?) any lsb errors.
So in theory you may be able to detect it or even measure it with state of the art equipment, in the real world - actually listening to music, you won't.
Yes. In my way of thinking 0x8001 is full-scale negative, 0x8000 I consider to be NaN (not a number) because it has no inverse (negative) within the 16bit number system. If its counted as valid then the space available for representing signals is asymmetric.
Don't forget that 2s complement is just the I2S signal format entering the DAC. It will be converted back to the natural OB (offset binary) format internally. It is 1-to-1 conversion, 2C 8000 (-32768 decimal) will convert to OB 0000. So 8000 is an existing value, this is the lowest number. Its inverse is 7FFF (+32767 decimal) is the highest number.
There are 32768 steps in the positive domain (0000 to 7FFF, 0 to 32767) and 32768 steps in the negative domain (FFFF to 8000, -1 to -32768). The range is symmetrical, because as I concluded above, the analog zero plus some noise converts to alternating 0 and -1 with 50%-50% probability.
I didn't see a conclusion above, rather I saw a claim. You claimed 'there's no round up, just truncation'. What did you base that claim on? You then continued as if you weren't quite sure of your claim. As far as I'm aware, digital silence is not at -0.5LSB, rather its at zero. If there's dither employed, why would it be biassed in the negative direction?
What you said about DACs may or may not be true, depending on their internal architecture. I doubt very much that those where there's a claim of 'no glitch around zero' use offset binary internally. Perhaps you'd get some ideas from reading the datasheet of Ti/BB PCM63.
What you said about DACs may or may not be true, depending on their internal architecture. I doubt very much that those where there's a claim of 'no glitch around zero' use offset binary internally. Perhaps you'd get some ideas from reading the datasheet of Ti/BB PCM63.
I meant the change from 0000 to 0001 (1 LSB) does happen at 1 LSB voltage, not at 0.5 LSB voltage. So everything between 0 and 1 LSB voltage converts to 0000. But this is not the case in negative direction: everything between 0 and -1 LSB voltage converts to FFFF. If there were rounding up, a signal between 0 and -1/2 LSB would convert to 0000, and a zero analog signal plus some noise would convert to 0000. Now it is converted to alternating 0000/FFFF, as if the zero were shifted by 1/2 LSB.
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