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#1 |
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diyAudio Member
Join Date: Dec 2007
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With the PC route, how can jitter be reduced?
Esp as jitter sensitivity increases with higher sample rates . . I've done some searching, but found nothing conclusive
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a system that won't go clean and loud is like a nice car that cannot go fast |
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#2 |
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diyAudio Member
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Hi, The switching power supply in a PC has very high EMI noise. So the digital audio signal from it usually comes with very high jitter level, even if you have a good clock osc inside. The best way is replacing the recovered clock with a new low jitter local clock to feed the DAC. I am just cooking a I2S FIFO project new, hopefully there would be some help. Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter
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#3 | |
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diyAudio Member
Join Date: Sep 2007
Location: Hangzhou - Marco Polo's 'most beautiful city'. 700yrs is a long time though...
Blog Entries: 46
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Quote:
Jitter gets into SPDIF because every link between transmitter and receiver is necessarily band-limited. This band-limiting causes inter-symbol interference and hence modulation of the transition points from which the clock is inferred by the receiver. Can't be avoided so there's a need for a decent clock recovery circuit to achieve low jitter.
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#4 | |
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diyAudio Member
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Quote:
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