Another TDA1541A based dac (dual differential)

[studiostevus]

Originally Posted by batteryman

A simplistic view would be (using a 1541 per channel as Tazzz recommends) and considering one channel:
Inputs: L & -L (-L = L data inverted)
Ouputs L + noise and -L + noise.

Subtract in a bifilar wound I/V transformer (swap start and end of one winding to achieve this) results in:
L- -L = 2L and because the noise was added within the dac,
noise - noise = no noise (well, less noise!)

that is, if the majority of dac noise is 'systematic'. Random noise generated by the dac and added circuitry (eg logic) is actually doubled.

On a separate subject:
What are the consequences of inserting an LC filter with an f-3 of about 15-16kHz* between the 1541 outputs and I/V transformer?

As the impedance needs to kept very low, use of an inductor should be practicable. (Sowter suggest a 200R load resistor on the dac output)

*my ancient ears probably don't work above 12-15KHz!
I

Phase shift is probably more detrimental to the sound than roll-off, no?

[batteryman]

Originally Posted by studiostevus

that is, if the majority of dac noise is 'systematic'. Random noise generated by the dac and added circuitry (eg logic) is actually doubled.



Phase shift is probably more detrimental to the sound than roll-off, no?

I would suggest that the biggest noise component is not random but due to the internal switching so the overall result is less noise.
As one dac is used per channel, each pair of dac outputs should have (theoretically) the same amplitude and polarity of noise which will therefore cancel in the transformer.

[Tam Lin]

Originally Posted by batteryman

I am about to start on a dual differential 1541a dac. I am buffering and inverting the data to one dac and using a bifilar wound dual primary I/V transformer.

The plan is to use 3 pairs (in series) of 74hct14 hex inverters to buffer all three I2S lines borrowed from the inputs of the 7220. One dac will receive its data after only one inversion.

The HCT14 is not a buffer. If you need additional fanout, use a low-skew clock driver designed for that purpose. If you need drive for a long cable, use a differential clock driver designed for that purpose.

Consider the additional noise added by unnecessary gates switching at the same time. When the source of the sample clock changes state, a spike of noise and ground bounce is injected into the circuit. Moments later, before the noise has had a chance to dissipate, the first inverter receives the changing clock edge and inverts it. The Schmidt trigger references Vcc and ground to determine the trigger points but the reference is polluted with noise. Then, as it is changing state, the first inverter injects additional noise and ground bounce into the circuit, which, in turn, degrades the operation of the second inverter. Your buffer has degraded the clock signal and increased jitter. A single pico-gate is sufficient to invert one data line with minimal impact on the rest of the circuit.

Also, inverting the data to one dac is insufficient to create a proper differential output. You must negate each sample value otherwise you will add a DC offset. Transformers, like the 9545, work best when there is no DC offset.

[guido]

I'm getting flashbacks from this thread. DC yes, but not a lot (lsb). Allthough it goes wrong at one of the end values iirc. All discussed (a lot) before..

As the currents return to +5, it makes sense to use a diff setup. In theory the current going through +5 is then 0 (assuming a perfect dac), the changing audio currents that is. The offset current of the 1541 doubles, but that's only DC.

If you want to do the inverting properly, the best way is a dig. filter and use the 1541 in another mode (not i2s). In that way you can correctly invert the feed to one channel. or a lot of logic in a cpld or fgpa.

[studiostevus]

refer to

Building the ultimate NOS DAC using TDA1541A

post 3409

[Tazzz]

In case of the tda1541 one LSB would result in an offset current of 61nA I would think most any signal transformer could tolerate that.

2's complement inversion falls apart for the most negative number so the logic would also have to handle that case. Besides if the data is encoded with "real" or absolute zero at 0.5 lsb then its actually correct to only invert the data.

In any case I'm not losing any sleep over this.

[batteryman]

Originally Posted by Tam Lin

The HCT14 is not a buffer. If you need additional fanout, use a low-skew clock driver designed for that purpose. If you need drive for a long cable, use a differential clock driver designed for that purpose.

Consider the additional noise added by unnecessary gates switching at the same time. When the source of the sample clock changes state, a spike of noise and ground bounce is injected into the circuit. Moments later, before the noise has had a chance to dissipate, the first inverter receives the changing clock edge and inverts it. The Schmidt trigger references Vcc and ground to determine the trigger points but the reference is polluted with noise. Then, as it is changing state, the first inverter injects additional noise and ground bounce into the circuit, which, in turn, degrades the operation of the second inverter. Your buffer has degraded the clock signal and increased jitter. A single pico-gate is sufficient to invert one data line with minimal impact on the rest of the circuit.

Also, inverting the data to one dac is insufficient to create a proper differential output. You must negate each sample value otherwise you will add a DC offset. Transformers, like the 9545, work best when there is no DC offset.

I'm adopting Tazzz's suggestion of using a 1541 per channel and therefore in simultaneous mode. The data will be split into left and right for feeding to each 1541 - probably using hc02s like Audio Note and the AD1865.

From post 3409

I tested this dual-mono mode recently, using a simple I2S encoder that converts L/R to L/L for chip #1 and R/R for chip #2. Both chips receive same BCK and WS signals, only the DATA signal for each chip differs. I didn't use balanced mode so possible "issues" with inverting DATA wouldn't occur.

From post 3409..
I tested this dual-mono mode recently, using a simple I2S encoder that converts L/R to L/L for chip #1 and R/R for chip #2. Both chips receive same BCK and WS signals, only the DATA signal for each chip differs. I didn't use balanced mode so possible "issues" with inverting DATA wouldn't occur.

Interesting experiments ahead to see just what happens (audibly) with inverting the data.

[batteryman]

I couldn't wait to finish the dual differential design so decided to experiemtn with the I/V transformers.

I disconnected the existing opamp & filter components from an old Philips Cd471 and soldered an LC Tee* filter loaded by 150R to the 1541 outputs.

The Sowter transformer primaries were paralled and connected across the 150r load and the secondaries series connected and fed directly to the amps aux input.

*2x 1mh in series and 100n to ground from the midpoint (online calculators with F-3 at 16khz, Z = 100r produced 2 x 1mh and 200n which I did try)

Without the filter there were audible artifacts as expected, but vastly reduced by the filter without major loss of hf (to my old ears!) and certainly listenable to and not a fet, tube, opamp or transistor in sight!

[Tazzz]

Originally Posted by studiostevus

Mmmmm... Interesting. Can you attach a picture of the fft you refer to?

Here are two measurement on the output of the dac while its running a 1Khz sine at -60dbFS The measurement is first taken with the negative output shorted to ground at the output of the dac you can see it below:



Here is the same measurement again only this time its measured differentially.

[QSerraTico_Tico]

Pictures do not open, please attach to your message.