Jitter Reduction through Reclocking Units - what is the best Approach ??

[tiefbassuebertr]

By follow URLs and in the attached files you will find various schematic of reclocking units in front of the DAC IC.
I don't understand the individual pros and cons.
At first look the russian approach seems to be the best solution.
But I am not really sure.
Which of this examples is to prefer?

Digital decoding of biphase-mark encoded serial digital signals
Reproduction equipment for digital audio

[SoNic_real_one]

First one is based on D-flip-folps... Garbage, it will miss or repeat samples periodically, based on instaneous difference of frequencies (source and local). End result - higher distortions. Some people like them...
Second one is not a reclocking is just a classic SPDIF receiver connected to the PCM100 digital filter.
Last one is a schematic for slaving a transport to the DAC. Like that is gonna solve anything... th ejitter from the transport will still be preset at the output (without a bigger RAM buffer than the usual 2K) and DAC will just produce higher distortions than without "slaving".
All in all none of the above will offer "jitter reduction". If it was THAT simple (D-latches) all the industry would have already implemented that.

Contrary to the general belief, electronic engineers are not morons or memebrs of a secret conspiracy to produce bad sounding devices.

[erin]

Originally Posted by SoNic_real_one

Contrary to the general belief, electronic engineers are not morons or memebrs of a secret conspiracy to produce bad sounding devices.

Sonic, that should be on your signature.......

[wwenze]

Originally Posted by SoNic_real_one

Contrary to the general belief, electronic engineers are not morons or memebrs of a secret conspiracy to produce bad sounding devices.

So what should people that produce bad sounding devices be called?

[oshifis]

Some (most) companies spare a 10c D-flip-flop or capacitor if they can. Some (most) consumers do not notice the difference, because they are not in the position to compare.

[CopperTop]

It's not that trivial a problem to solve, unless you can control the flow of data from the source.

Here's a very interesting article on how to re-clock data from a USB stream using a PLL:

The D/A diaries: A personal memoir of engineering heartache and triumph

Or you can presumably go for the asynchronous sample rate conversion route, and re-sample the incoming data at the very slightly different clock rate of your DAC, but this would change the 'bits' - though in almost a theoretically perfect way. Something like this:
http://www.analog.com/en/audiovideo-...s/product.html

[DF96]

Originally Posted by SoNic_real_one

th ejitter from the transport will still be preset at the output (without a bigger RAM buffer than the usual 2K)

That is your (minority) opinion. The facts suggest otherwise. We have had that argument in another thread, so I'm not trying to carry it on here just alert people to the conventional view.

Most simple attempts at reclocking swap one form of jitter for another, typically much worse. Doubling or dropping of samples will happen. As you say, this leads to garbage yet it curiously seems popular.

Contrary to the general belief, electronic engineers are not morons or memebrs of a secret conspiracy to produce bad sounding devices.

Agreed, although those who have some experience of EEs while they are still students may feel that their education has significant shortcomings. They are taught to repeat the mantra "digital good, analogue bad" by their teachers, and as a result may have little interest in learning how to do good analogue circuitry and may be overly confident in the abilities of digital stuff.

[CopperTop]

Originally Posted by DF96

Most simple attempts at reclocking swap one form of jitter for another, typically much worse. Doubling or dropping of samples will happen. As you say, this leads to garbage yet it curiously seems popular.

You are kidding! People do this?!

As the links I posted above show, the problem is to all intents and purposes solved. It's not something I've ever tried to do, myself, although I sometimes have to 're-clock' other types of digital stream in my work (PLLs are things of beauty aren't they?).

Do CD transports ever provide an input to allow the DAC to regulate the flow of data - which would obviously be the simplest and best solution? Presumably this is what happens in the typical non-audiophile CD player that houses the transport and DAC together.

[DF96]

You are kidding! People do this?!

I believe it is known as asynchronous reclocking. The idea appears to be that as the derived clock from SPDIF is too horrible, simply substitute a local crystal clock at nominally the same frequency. No attempt is made to lock the clocks together. Drift will therefore mean either duplicated or dropped samples at the difference frequency rate - typically several times a second?

Having the DAC regulate data might be better, as up to the DAC output the timing does not matter too much - before that point the data is just that - data. However, the conventional solution tries to deal correctly with the problems: CDP-DAC link introduces high frequency jitter, which the receiver PLL eliminates. In addition, the clock recovery circuit uses the parts of the signal which are least likely to be corrupted. My guess is that most of the jitter seen by the DAC originates in the CD player clock, which is why improving the clock may be worth doing.

[Charles Darwin]

"PLLs are things of beauty aren't they?"

Not according to Dan Lavry, he should still have his white papers on his site explaining why PLLs are the spawn of the devil. Always use the DACs clock as the master.

Lavry Engineering - Unsurpassed Excellence