XMOS-based Asynchronous USB to I2S interface - Page 181 - diyAudio
Go Back   Home > Forums > Source & Line > Digital Source

Digital Source Digital Players and Recorders: CD , SACD , Tape, Memory Card, etc.

Please consider donating to help us continue to serve you.

Ads on/off / Custom Title / More PMs / More album space / Advanced printing & mass image saving
Reply
 
Thread Tools Search this Thread
Old 19th June 2013, 08:55 PM   #1801
JensH is offline JensH  Denmark
diyAudio Member
 
Join Date: Jul 2009
I assume that the two sides of the LVDS have each their own ground. Otherwise it wouldn't really make sense anyway
But will the generally good properties of the LVDS connection still be there?

I assumed that the clock for the XMOS was not terribly sensitive to jitter and duty cycle etc., but perhaps I am wrong?
  Reply With Quote
Old 20th June 2013, 07:53 AM   #1802
diyAudio Member
 
Join Date: Nov 2007
Quote:
Originally Posted by JensH View Post
I assume that the two sides of the LVDS have each their own ground. Otherwise it wouldn't really make sense anyway
Yes, there are two fully separated ground regions otherwise it would make no sense for me either
Quote:
Originally Posted by JensH View Post
But will the generally good properties of the LVDS connection still be there? I assumed that the clock for the XMOS was not terribly sensitive to jitter and duty cycle etc., but perhaps I am wrong?
At some point it does not really matter anymore as there's the reclocking stage after the XMOS processor. Even so, when it comes to jitter LVDS is my preferred choice and I thought that, if I can, it would be better to try and improve all the clock chains, including this XMOS feeding one.
Kind regards,
L
__________________
Contact link for WaveIO USB-to-I2S/SPDIF board.
Daughter card GB list for WaveIO can be found here
  Reply With Quote
Old 20th June 2013, 08:58 AM   #1803
JensH is offline JensH  Denmark
diyAudio Member
 
Join Date: Jul 2009
In my work I am often invelved in trying to identify problems at an early stage so that they can be corrected before the consequences become too big. But perhaps I am just seeing ghosts here, and there are no problems.

You could of course also consider a backup solution, e.g. a TI ISO7220M or similar. With this one there would also be a return path for the input data channel
  Reply With Quote
Old 20th June 2013, 09:34 AM   #1804
diyAudio Member
 
Join Date: Nov 2007
I simply squeezed my brain to find a viable solution here so far this is the best I can think of. I am aware about the fact that there are isolators with four channels (3 + 1) still when you have four signals following the same path (I2S bit Clock / I2S Word Clock / I2S Data / Oscillator Select) and the XMOS clock needed to follow the opposite path then the four way isolator is simply not enough
Five channels or more is too expensive in this case.
As for ISO7220M, it is already taken into account, thank you for the tip
Cheers,
L

Edit:
Quote:
But perhaps I am just seeing ghosts here, and there are no problems.
Hmm, hard to believe! I simply wish to be this way.., but these days I'll find out what I've done
__________________
Contact link for WaveIO USB-to-I2S/SPDIF board.
Daughter card GB list for WaveIO can be found here

Last edited by Lorien; 20th June 2013 at 09:41 AM.
  Reply With Quote
Old 24th June 2013, 06:41 PM   #1805
diyAudio Member
 
Join Date: Jul 2010
Default ESS clock rates follow up

Lorien,

To follow up on the clock rates discussion for best compatibility with synchronous operation of ESS based DACs, found the relevant information. The ESS needs masterclock at >192 Fs and synchronous/in phase with bit clock. So for proper performance with ESS based DACs you would want to provide 45.1584 and 49.152 masterclock frequencies for playback of 24/176.4 and 24/192 files.
No need to respond to this, I just wanted to get you the information.
  Reply With Quote
Old 24th June 2013, 11:12 PM   #1806
JensH is offline JensH  Denmark
diyAudio Member
 
Join Date: Jul 2009
I don't think the master clock needs to be in phase with the bit clock, but I think it will be an advantage to keep it locked in frequency.
  Reply With Quote
Old 24th June 2013, 11:44 PM   #1807
diyAudio Member
 
Join Date: Jul 2010
Default my...

Quote:
Originally Posted by JensH View Post
I don't think the master clock needs to be in phase with the bit clock, but I think it will be an advantage to keep it locked in frequency.
understanding is that to take advantage of synchronous clocking on the ESS, the Master Clock and the Bit Clock must be in phase. The point is to keep the ASRC/DPLL from being active-my opinion is that it sounds better this way (assuming a very low jitter source). But this should be the case anyway if the output data (I2S) is re-clocked by the MC just before output as Lorien is saying, right? Or am I misunderstanding something?
  Reply With Quote
Old 25th June 2013, 12:12 AM   #1808
1audio is offline 1audio  United States
diyAudio Member
 
Join Date: Mar 2004
Location: SF Bay Area
Blog Entries: 3
Usually there will be a spec for timing between the master clock edge that matters and the bit clock edge that matters. It will be tight since the clock has a 20 nS period so gate delays etc. will be critical. There may also be registers in the chip where you can lock the mode of operation. Finding those registers will be a challenge if they aren't in the datasheet.
__________________
Demian Martin
Product Design Services
  Reply With Quote
Old 25th June 2013, 12:31 AM   #1809
qusp is offline qusp  Australia
diyAudio Member
 
qusp's Avatar
 
Join Date: Oct 2009
Location: Brisbane, Australia
actually barrows, all info i've seen oft' repeated and from my own experience, its the opposite, inverted Mclk. thats why this was provided as the default on the fifo Si570 board (though you can choose)
  Reply With Quote
Old 25th June 2013, 06:59 AM   #1810
diyAudio Member
 
Join Date: Nov 2007
Quote:
Originally Posted by barrows View Post
Lorien,

To follow up on the clock rates discussion for best compatibility with synchronous operation of ESS based DACs, found the relevant information. The ESS needs masterclock at >192 Fs and synchronous/in phase with bit clock. So for proper performance with ESS based DACs you would want to provide 45.1584 and 49.152 masterclock frequencies for playback of 24/176.4 and 24/192 files.
No need to respond to this, I just wanted to get you the information.
Thank you Barrows! Your help is highly appreciated!

Quote:
Originally Posted by JensH View Post
I don't think the master clock needs to be in phase with the bit clock, but I think it will be an advantage to keep it locked in frequency.
I thought at that too but I'm still not convinced about the synchronicity of those signals.

Quote:
Originally Posted by barrows View Post
understanding is that to take advantage of synchronous clocking on the ESS, the Master Clock and the Bit Clock must be in phase. The point is to keep the ASRC/DPLL from being active-my opinion is that it sounds better this way (assuming a very low jitter source). But this should be the case anyway if the output data (I2S) is re-clocked by the MC just before output as Lorien is saying, right? Or am I misunderstanding something?
Well, reclocking is the main idea and I had do it as the XMOS is a mess. Even so, I liked to have the Master clock in sync but this means to divide it by 2. Anyway, the downside is that NDK oscillator family that I'm using now (NZ2520SD) are not able to source clocks higher than 60 MHz so 90s freqs. are out of the question. Given this, I somehow have to manage all this by using the 45.1584 and 49.152 masterclock freqs. One solution would be to buffer the master clock and make sure that the buffer delay will be close to the FF delay (but I already know that it's hard to achieve...)

Quote:
Originally Posted by 1audio View Post
Usually there will be a spec for timing between the master clock edge that matters and the bit clock edge that matters. It will be tight since the clock has a 20 nS period so gate delays etc. will be critical. There may also be registers in the chip where you can lock the mode of operation. Finding those registers will be a challenge if they aren't in the datasheet.
I am fully agree with you but beating the ESS DACs to death could be fun for most of us and lead to redesigning the entire chip if needed Anyway, I am simply relying on the ESS designer's work here hoping that they knew what they were doing in that chip.

Quote:
Originally Posted by qusp View Post
actually barrows, all info i've seen oft' repeated and from my own experience, its the opposite, inverted Mclk. thats why this was provided as the default on the fifo Si570 board (though you can choose)
Huh, inverted MCLK now...
I have to start looking for an inverter and a buffer in the same package just to be able to switch the chips in case that needed.
Thank you,
L
__________________
Contact link for WaveIO USB-to-I2S/SPDIF board.
Daughter card GB list for WaveIO can be found here
  Reply With Quote

Reply


Hide this!Advertise here!
Thread Tools Search this Thread
Search this Thread:

Advanced Search

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are Off
Pingbacks are Off
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
exaU2I - Multi-Channel Asynchronous USB to I2S Interface exa065 exaDevices 1357 3rd March 2014 09:51 PM
Introducing miniStreamer: Native 24/96 USB to I2S / SPDIF interface minidsp miniDSP 39 6th January 2014 12:00 AM
Ultimate USB to I2S interface sampler Digital Source 206 30th January 2012 04:45 PM
Is it possible to develop a ASIO driver for PCM2900 based USB Audio interface? cxhawk Digital Source 7 3rd December 2010 03:30 PM
interface I2S with USB mermoz Digital Source 0 21st February 2003 11:34 AM


New To Site? Need Help?

All times are GMT. The time now is 04:06 AM.


vBulletin Optimisation provided by vB Optimise (Pro) - vBulletin Mods & Addons Copyright © 2014 DragonByte Technologies Ltd.
Copyright ©1999-2014 diyAudio

Content Relevant URLs by vBSEO 3.3.2