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Old 1st November 2011, 12:27 PM   #151
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His point was perfectly clear to me
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Old 1st November 2011, 12:27 PM   #152
Turbon is online now Turbon  Sweden
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Now we are moving. What is jitter (we know this)? How much were allowed if quantification methods were available at the time on implementation? If not, what is the best method to measure it so it would be understandable by the average buddy/Joe/Clarissa (me:-))

Brgds
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Old 1st November 2011, 12:35 PM   #153
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Originally Posted by abraxalito View Post
His point was perfectly clear to me
OK, elucidate it.

Let's face it, you two are simply seeking to dispute with anybody you think might be competent to put up a good argument.
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Old 1st November 2011, 12:37 PM   #154
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Originally Posted by counter culture View Post
OK, elucidate it.
You're trolling. Is that clear enough?
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Old 1st November 2011, 12:38 PM   #155
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No, I'm not.
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Old 1st November 2011, 12:42 PM   #156
Turbon is online now Turbon  Sweden
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Now, c'mon friends. We are probably all twisting strings on subjects where there are no commonly agreed answers yet. Thats a definition to me of an emerging standard...

The first step would be to bombard MS with request for a uac2 common driver and build the hw from there.

Yupp, I have sent my wishes to ms. Whatever they decide will of course set the baseline even if we know better ;-)

Brgds

Last edited by Turbon; 1st November 2011 at 01:05 PM.
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Old 1st November 2011, 02:48 PM   #157
Bunpei is offline Bunpei  Japan
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Now we are moving. What is jitter (we know this)? How much were allowed if quantification methods were available at the time on implementation? If not, what is the best method to measure it so it would be understandable by the average buddy/Joe/Clarissa (me:-))
I do not favor the term "jitter", but "phase noise".

You can look at "phase noise plot" on this page.
phase noise definition
In this example, the plot is for a master clock.
I wish we could measure a phase noise for MCLK, LRCLK, BCLK signal of I2S just at input pins of DAC chip.
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Old 1st November 2011, 03:56 PM   #158
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Default I2S and async USB...

1. For I2S you have: data, bit clock, word clock, and master clock:

Some DACs, will not need masterclock, as they will be using their own and reclocking-aligning the master clock to the bit clock. But best performance will be realised with one oscillator producing both the masterclock and bit clock, so that no realigning (PLL) is needed, as long as the provided clock is low in phase noise.

2. For I2S the sender does not have to be the master. For example, again the Ayre QB-9: the two oscillators are on the DAC board, close to the DAC chip, and then the master clock signal is sent back over I2S to the USB receiver (which is XMOS based). The DAC board is powered by a separate supply from the USB receiver board, hence the oscillators get a clean supply.

Lorien, could the new rev be made with the option to accept masterclock in to accommodate the approach used in "2" above?
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Old 1st November 2011, 05:17 PM   #159
reo is offline reo  Canada
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hi folks
little off beat question... but necessary for me to join my buffaloII with WaveI/O.
WaveI/O has outputs provision of MCLK, LRCLK, BCLK and DATA , now where do they in relation with the BuffaloII inputs of the I2S, there the SCL,SDA, GND,and DVCC .,
i don't understand the abreviation of those terms that are used for the I2S inputs on the Buffalo dac , i looked and looked but to no avail .
any help is appreciated .
regards
rols.
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Old 1st November 2011, 06:06 PM   #160
reo is offline reo  Canada
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Quote:
Originally Posted by reo View Post
hi folks
little off beat question... but necessary for me to join my buffaloII with WaveI/O.
WaveI/O has outputs provision of MCLK, LRCLK, BCLK and DATA , now where do they in relation with the BuffaloII inputs of the I2S, there the SCL,SDA, GND,and DVCC .,
i don't understand the abreviation of those terms that are used for the I2S inputs on the Buffalo dac , i looked and looked but to no avail .
any help is appreciated .
regards
rols.
apology ...wrong forum .
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