XMOS-based Asynchronous USB to I2S interface

[luisbock]

Lifepo4

[JLOP]

Hi all

To connect the Wave IO board to my DAC AD1865 NOS SRPP (which has no connector yet and when Lucian will have done the software update to allow for RightJustified I2S this DAC has ), I am looking for advices :
- what connectors (DEP, 8P8C RJ45, ...) ?
- what cables (shielded, not shielded, CAT5 or 6, flat, ...) ?

Thanks
Jean-Louis

[jrling]

Originally Posted by luisbock

Lifepo4

I do agree that they are the best battery power technology, but the cells are 6.6v (2S) and we want 5.0VDC for the WaveIO.

So some sort of regulation will be required.

The phone charger type LiPOs do output at 5V and would have no charger noise if not plugged into the mains. So convenience factor very high and effectively Plug 'n Play.

[Sandor]

I am connecting the I2s output of the WaveIo board to the I2S input of a Buffalo II DAC. I know that a mod is required to feed the buffalo II with the master clock.

1) What benefit can I expect from feeding the DAC with the WaveIO master clock?

2) Is it necessary to connect the WaveIO master clock to the Buffalo (i.e. do the mod) to have the USB->I2S conversion work in true asynchronous mode ?

Thanks a lot.

[hochopeper]

Originally Posted by Sandor

I am connecting the I2s output of the WaveIo board to the I2S input of a Buffalo II DAC. I know that a mod is required to feed the buffalo II with the master clock.

1) What benefit can I expect from feeding the DAC with the WaveIO master clock?

Hard to say ... it depends really. From what I have read mostly the benefits come if you are able to provide a high freq master clock, closer to 100MHz. With the WaveIO clocks you won't get high enough for it to be worthwhile IMO.

Originally Posted by Sandor

2) Is it necessary to connect the WaveIO master clock to the Buffalo (i.e. do the mod) to have the USB->I2S conversion work in true asynchronous mode ?

Thanks a lot.

If you don't mod the BII and just connect I2S without the mclk from the WaveIO you will have asynch (clock is provided by the one mounted to the BII).

The mod is required for synchronous mode.

[barrows]

Originally Posted by Sandor

I am connecting the I2s output of the WaveIo board to the I2S input of a Buffalo II DAC. I know that a mod is required to feed the buffalo II with the master clock.

1) What benefit can I expect from feeding the DAC with the WaveIO master clock?

You will have to listen and see. Synchronous clocking disables the asynchronous sample rate converter and the DPLL. So it allows the digital data to go direct to the oversampling filter and delta sigma modulator of the ESS chip unchanged. I generally do not like the sound of asynchronous sample rate converters (although the ESS' sounds a lot better than most others to me) and feel that synchronous clocking with my B-II sounds more natural. The clocks on the Wave IO will work with the proper spec from ESS for data rates up to 24/96, according to ESS, it would be better to have x2 clocks for 176.4 and 192 rates, but it will work fine with the clocks on the Wave IO. I am running my B-II in synchronous mode from clocks of the same rate as those on the Wave IO, and I like the sound better than running the B-II using the onboard MC. The previous poster's advice concerning 100 mHz clocks is not correct, as that rate is for running the ESS in asychronous mode. But according to ESS, it would be "better" to have 2x clock rates for 176.4 and 192 (and 4x rates if one is trying to playback 352.8 and 384 files)

2) Is it necessary to connect the WaveIO master clock to the Buffalo (i.e. do the mod) to have the USB->I2S conversion work in true asynchronous mode ?

The Wave IO interface will always operate asynchronously regardless of how you provide clocking to the ESS chip itself. The difference is: if you run the B-II using the onboard master clock, then the DAC chip itself has its asynchronous sample rate converter active, if you run the B-II using an external masterclock from the Wave IO, then the onboard clocking of the DAC chip is synchronous, that is, the masterclock and bit clock are synchronous with each other and the asynchronous sample rate converter will be inactive. Either way, the Wave IO is still operating asynchronously.

Thanks a lot.

[qusp]

it doesnt bypass the pll and go straight to the modulator, nothing changes internally in the ESS, there is no switch, no change in the signal path, its all the same, but if running synchronously it just effectively has nothing to do. the DPLL is 'freewheeling' to use Dustins words. also hochopeper said closer to 100MHz, not actually 100MHz. I guess he just couldnt be bothered typing out the exact numbers of 90.3168Mhz/98.304MHz (<-pretty close to 100MHz dont you think?)

[barrows]

Originally Posted by qusp

it doesnt bypass the pll and go straight to the modulator, nothing changes internally in the ESS, there is no switch, no change in the signal path, its all the same, but if running synchronously it just effectively has nothing to do. the DPLL is 'freewheeling' to use Dustins words. also hochopeper said closer to 100MHz, not actually 100MHz. I guess he just couldnt be bothered typing out the exact numbers of 90.3168Mhz/98.304MHz (<-pretty close to 100MHz dont you think?)

right: because the masterclock and the bit clock are synchronous, both the onboard ASRC and DPLL do nothing to the data, so the data passes through those parts of the DAC chip without being changed at all. Hence, it is the same as if there was an internal "switch" actually changing the signal path.
As I said-the data goes straight to the OSF and DSM without being changed by the ASRC and DPLL.

The ESS spec calls for the clock rate to be >192 fs, so for a 192 sample rate that means >36.864 MHz, quite a bit lower than the 100 MHz he mentioned. To meet ESS specs for best operation at up to 192 (the highest rate wave IO allows) 2x clocks would be totally fine: 45.158 and 49.152, not close to 100 MHz at all. That being said, I am running an XMOS based async interface, with 22.579 MHz and 24.576 MHz clocks, the same as the Wave IO's, and it works fine (and sounds better synchronously) with music playback of files at sample rates up to 192. According to ESS, it should sound even better with 2x clocks, I have not heard that yet, but still running the B-II synchronously even with the lower rate clocks sounds better than using the onboard masterclock.
Now, if one wants to meet the ESS data sheet, and support sample rates up to 384, then a masterclock "around 100 MHz" would be required (4x rate, or >192*384=>73.728 MHz). But the Wave IO does not support sample rates above 192.
My point is, that one should not be discouraged from trying synchronous clocking with the Wave IO's standard clocks, they meet the ESS requirements for rates up 96 KHz, and they will also work fine for rates up to 192 KHz. Listen, and decide for oneself.

[hochopeper]

Are we going to have the same discussion on a monthly basis guys? Post#1155 onwards has the same discussion again. Sandor, you might gain something by looking at those posts too.

[qusp]

not going to continue, just correcting the error, which I did, I have no desire to enter into conversation about it, or argue about irrelevent additional details, since it seems not to sink in anyway.