Open-source USB interface: Audio Widget

[borges]

Originally Posted by starn02

Can anybody describe a little how the connection between the Atmel MCU and the es9023 is implemented?
From the schematics I see (if I'm not mistaken) that the clock to the es9023 comes directly from crystals, while the other signals (data, LRClock and SCLK) come from the MCU .... What about timing synchronization between the clock and the SSC the MCU ? Aren't there jitter or delay problems between the signals?

The clock from the XOs branches in two. One branch goes directly to the DAC, the other to a divice-by-two flip-flop and into the MCU. The MCU can't handle the high 22-24MHz MCLK frequency directly.

The MCU uses I2S to talk to the DAC. You need both schematics in front of you to trace through the module interface.

It so happens that the bit clock of the I2S bus is the same signal as the divided-by-two MCLK which enters the MCU. This gives enough ticks for stereo 32-bit data at 192. Bumper-to-bumper I2S can be risky, so 24-bit data to the DACs is preferable.

Børge

[MrSlim]

Hmm.. you've got me thinking now.. I already have a AMB Gamma2 (using a WM8741) (and the parts for a second one...) that I could feed I2S directly into from an Audio Widget(the Gamma2 has an input header for I2S). Can I2S be easily tapped into on either of the boards?

[borges]

Originally Posted by MrSlim

Hmm.. you've got me thinking now.. I already have a AMB Gamma2 (using a WM8741) (and the parts for a second one...) that I could feed I2S directly into from an Audio Widget(the Gamma2 has an input header for I2S). Can I2S be easily tapped into on either of the boards?

Yes, you can latch onto the half-moon pads on the edge of the module. There's no dedicated I2S header. (Hint to self for revised layout...)

Børge

[qusp]

Originally Posted by alexlee188

A glimpse into the internals of Sabre DAC's:

http://www.esstech.com/PDF/sabrewp.pdf

Alex

I had skimmed this before, but i hadnt noticed this very nice and rather logical description of the intrinsic audible effect of jitter

Originally Posted by ESS

The noise that jitter induces is not easily described: it is not a harmonic
distortion but is a noise near the tone of the music that varies with the music: it is a noise that surrounds each frequency present in the audio signal and is proportional to it. Jitter noise is therefore subtle and will not be heard in the silence between audio programs. Experienced listeners will perceive it as a lack of clarity in the sound field or as a faint noise that accompanies the otherwise well defined quieter elements of the audio program.

[starn02]

Originally Posted by borges

The clock from the XOs branches in two. One branch goes directly to the DAC, the other to a divice-by-two flip-flop and into the MCU .... the bit clock of the I2S bus is the same signal as the divided-by-two MCLK which enters the MCU.

Wouldn't it be possible to configure the I2S so that we feed the clock to the bit clock of the I2S bus instead of letting this signal pass through all the MCU? I guess that the signal is formally the same, but in practice in the actual setup we get an output bit clock that is much less "clean" with respect to the clock coming from the divider ...

[borges]

Originally Posted by starn02

Wouldn't it be possible to configure the I2S so that we feed the clock to the bit clock of the I2S bus instead of letting this signal pass through all the MCU? I guess that the signal is formally the same, but in practice in the actual setup we get an output bit clock that is much less "clean" with respect to the clock coming from the divider ...

I believe so, but it's better to let the MCU's shift registers manage set-up and hold times. Besides, the DAC requires clocks in the 22-24MHz range whereas the MCU copes with 11-12. I don't trust a flip-flop to not introduce jitter, and XOs at 11.2896/12.288MHz aren't compatible with the two highest sample rates.

The MCLK passes directly to the DAC anyway. In a perfectly logical world, MCLK clocks the sigma-delta modulator and current switches.

The PCM1704 is a different story. This DAC doesn't have an MCLK input pin. Instead this multibit converter does 24-bit parallel latching on the 4th (or 2nd?) bit clock tick after word clock. So in that design, the bit clock comes straight from the XO and everything else slaves it.

Børge

[borges]

Hi guys,

here's a thread to the AVR forum where I asked what has to be done electrically in order to use the USB-I2S module with a mains powered DAC.

View topic - USB self powered :: AVR Freaks

Merry Christmas everyone!

Børge

[Turbon]

Now it's Christmas - if we have been nice we can have whatever we want...

For a starter - Yes - I want a 24/192 driver to a reasonable cost. If not I will do whatever it takes to help writing one and it will be free - sorry - no money in this one.

But now, why put this effort in something that will be the standard offering in a short while? The frontbreatchers is on 32/384 or whatever now. So the free (as in no pay) driver for the audio-widget should have atleast the stubs built in for the future. The model should be likely as free - pick whatever - and write some code (as our best knowledge and support on everyones time they want to put into the project) and you be all set to use whatever MCU or technology you desire as long it plays with these ideas. I couldn't write terms since I'm have no idea of the others view of where the audio-widget is heading in commercial terms.

And of course I beg you all a very Merry Christmas!

Brgds

[starn02]

Hi guys,
I miss the complete datasheet of ES9023, so I wonder what's the reason behind the choices of capacitor around it.
I see a generic approach based on a parallel of: 4n7, 1u, 10u, 15u ... some of them installed, some not, for AVCC, VREG, NEG e between CN and CP.

I understand that some of the places on the board are simply for testing, but are there limits for some of the pins?

For charge pump capacitor (which I suppose is the one between CN and CP) are there suggested or limit values? Actually I have 1u in parallel with 4n7. Can I use also 15u?

And the 4n7 capacitors are to be considered as bypass? Why not the more common value of 100nF?

[Turbon]

Originally Posted by starn02

Hi guys,
I miss the complete datasheet of ES9023, so I wonder what's the reason behind the choices of capacitor around it.
I see a generic approach based on a parallel of: 4n7, 1u, 10u, 15u ... some of them installed, some not, for AVCC, VREG, NEG e between CN and CP.

I understand that some of the places on the board are simply for testing, but are there limits for some of the pins?

For charge pump capacitor (which I suppose is the one between CN and CP) are there suggested or limit values? Actually I have 1u in parallel with 4n7. Can I use also 15u?

And the 4n7 capacitors are to be considered as bypass? Why not the more common value of 100nF?

I believe Alex played with the caps according to some older posts in the google audio widget group. Fo myself - I haven't even given them a thought since the driver comes first as I see it. My next move is to read a book or two about windows drivers during my winter vacation. If I can find any until tuesday!

Now the only book I found won't be shipped fast enought. Does anyone know about a bookshop in Miami who might sell books from MS Press? Do they have the book about drivers?

Brgds