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Old 23rd December 2011, 06:35 AM   #601
starn02 is offline starn02  Italy
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Can anybody describe a little how the connection between the Atmel MCU and the es9023 is implemented?
From the schematics I see (if I'm not mistaken) that the clock to the es9023 comes directly from crystals, while the other signals (data, LRClock and SCLK) come from the MCU .... What about timing synchronization between the clock and the SSC the MCU ? Aren't there jitter or delay problems between the signals?
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Old 23rd December 2011, 07:47 AM   #602
borges is offline borges  Norway
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Quote:
Originally Posted by rsdio View Post
When designing USB boards, I place the ferrite beads on the PCB so that it works equally well for all cables. I realize it's too late to modify boards in the field, but if you revise the PCB then I suggest adding ferrite beads and other appropriate filtering on the PCB.
Please follow the link from my signature and look at the module schematics. L1006 and L1007 are between USB VBUS/GND and those on the board.

The components are 0603. If you suggest any alternative components, please let me know! The ones used I copied from an unrelated USB design.

Oh, and if the sch/layout could be improved on, let us know about that too.


BÝrge
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Old 23rd December 2011, 09:27 AM   #603
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OK. This is a brief description and discussion of the clock signals in the audio-widget. If anyone is interested in the details and rationale and scope tracings etc., join the sdr-widget and audio-widget Google groups and search the archives :-)

The most important ultra low jitter clock is the MCLK to the DAC. This is achieved in the AW by clocking the ES9023 directly with either the 24.576Mhz or the 22.5792Mhz XO, selectable by the uC.

The i2S clock inputs to the DAC, ie SCLK and LRCK, has to be *synchronous* to the MCLK, but the phase relationships and jitter tolerances are much more flexible (as we have found out). This is because the SCLK/LRCK are used to clock digital data into the DAC's internal registers. How and when the data is "clocked" out by the sigma delta demodulator is governed by the MCLK.

To ensure that SCLK/LRCK are synchronous to MCLK, they are derived from the MCLK.

The MCLK is divided by 2 by a flip-flop (which incidentally also acts as a buffer between the MCLK/DAC circuitary and the digital uC circuitary), and fed into the Osc 1 input of the Atmel uC.

Using the uC's programmable generic clock dividers and the SSC's programmable dividers, the correct SCLK/LRCK signals and the corresponding SDATA are generated based on the i2S protocol timing and rise/fall edges etc.

You will not be able to do this with some DAC's that do not have a MCLK, and relies on the SCLK for precise timing.

Alex
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Old 23rd December 2011, 10:57 AM   #604
starn02 is offline starn02  Italy
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Alex, thank you so much for the explaination.
My main problem now is that I have only the 2 page datasheet about es9023, no details about signals ....
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Old 23rd December 2011, 11:54 AM   #605
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A glimpse into the internals of Sabre DAC's:

http://www.esstech.com/PDF/sabrewp.pdf

Alex
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Old 23rd December 2011, 02:41 PM   #606
UnixMan is offline UnixMan  Europe
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Quote:
Originally Posted by starn02 View Post
My main problem now is that I have only the 2 page datasheet about es9023, no details about signals ....
It looks like the "Sabre" DAC designs are rated "top secret" by ESS. Apparently no one but ESS has more than those two pages.

Only for the old ES9008 a somewhat more detailed data-sheet have been leaked out. You may want to refer to that: I guess there have been not too much "external" changes. Actually, the 9023 may even be directly derived from it.

Have a look at this thread: ESS Sabre Reference DAC (8-channel)

(and in particular pay attention to the posts from "dusfor99" alias Dustin Foreman, which is one of the designers of the "Sabre" DAC).
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Last edited by UnixMan; 23rd December 2011 at 02:44 PM.
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Old 23rd December 2011, 02:44 PM   #607
borges is offline borges  Norway
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I'm voting for TI and Wolfson. They make sense of support, samples, datasheets etc.

I say it's better to use a good DAC we can utilize fully, than an ESS device where we are fumbling around in the dark. The ES9023 is a simple device. The ES9018 has IVC and PSU needs I don't wish to experiment around. Since they, for all practical purposes, are not documented, it's no fun working with that chip.

BÝrge
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Old 23rd December 2011, 02:49 PM   #608
starn02 is offline starn02  Italy
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and how is anybody supposed to design a board using ESS chips?
By copying existing designs ... or they will give him a ten pages datasheet after he buys 1 million chips?
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Old 23rd December 2011, 02:52 PM   #609
adelias is offline adelias  Greece
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All you need to do is email the ESS distributor, Shaw Electronics, and ask for a copy of the datasheet.
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Old 23rd December 2011, 03:14 PM   #610
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It is interesting to note that the "ESS Sabre Reference DAC (8-channel)" thread guys are talking about:

"Synchronous MCLKing scheme for ES9018"

recently :-)

Alex
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