Open-source USB interface: Audio Widget - Page 31 - diyAudio
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Old 27th October 2011, 09:40 AM   #301
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Join Date: Apr 2011
There is a ring buffer in the widget firmware. So when sync is lost the buffer is replayed.

Uac1 and uac2 have very different mechanisms and the drivers will also behave differently.

I will look at uac1 mute and see whether there are ways to mute the "chirps". You cannot compare the widget against other uac1 devices as they may not be (unlikely) async out with rate feedback. If there is no rate feedback there is no loss of sync to speak of :-)

Playback software should also do the proper thing by muting the output while skipping tracts or changing sampling rates etc.

Nonetheless, I will see what can be done in the firmware to mute the output :-). If in cannot be done u can always stick with uac2 :-)

Alex
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Old 27th October 2011, 10:30 AM   #302
borges is offline borges  Norway
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Hi Alex,

I'm glad my suspicions aren't too far afield. I've tested with UAC1 + Win + VideoLanClient (VLC) player. The issue sounds the same across multiple win versions.
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Old 27th October 2011, 10:25 PM   #303
prh is offline prh
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Can I apologize in advance, as I have not read this whole thread.

I am interested in an I2S to usb device (up to 24/192) to take digital audio into a PC.

I am starting a project to rack up a TI PCM4222 ADC evaluation board, and want to capture the digital audio to computer. The evaluation board has a serial data header from which an I2S format data stream can be taken.

(I have found some options (eg the miniSTREAMER) which offer up to 24/96, and I could also just use the spdif input from my Echo Audiofire 8 interface.)

Just wondering if any of the projects discussed here can be used, or adapted, for my purpose? Thanks in advance.

regards, Paul
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Old 27th October 2011, 11:16 PM   #304
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See schematics and details of the sdr-widget:

Yoyodyne Consulting/SDR-Widget

You will find how the AK5394A ADC is wired up for 48/96/192khz 24 bit capture.

To adapt the USB-I2C to another ADC will require some hardware and firmware development work by the user.

Alex
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Old 28th October 2011, 09:36 AM   #305
borges is offline borges  Norway
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Hi guys, how difficult would it be to add firmware for generic ADC I2S to the audio widget branches? The ADC would have to be I2S slave. And whether or not to forward the data from the I2S pin (and enumerating as audio IN for that matter) could be a matter of firmware config. The hardware support is already there.

BÝrge
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Old 28th October 2011, 11:47 AM   #306
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Hi Borge,

The ADC will have to be i2s master instead of slave to make sure the L/R channels are not inverted. This is a quirk of the Atmel chip (we are using the DMA for the i2s transfers and the exact timing with respect to the LRCK is not directly controllable by the cpu.)

Also the MCLK for the ADC has to be synchronous with the i2s clock used by the Atmel - ie you need to feed the MCLK (or a divided MCLK in case it is > 16Mhz, as the Atmel uC cannot take > 16Mhz) to the Atmel's xin1 pin.

If you want the ADC to be i2c slave, you will have to have a master clock and clock circuit that can generate the i2s SCLK and LRCK and then drive both the ADC and the Atmel. This is not trivial as the LRCK freq changes with the sampling rate.

In other words, you have to look at each ADC and see how best to design the hardware/firmware to fit. A "generic" ADC interface may not give you the low jitter clock signals and consistent L/R channels desired for a high performance unit.

Alex
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Old 28th October 2011, 11:52 AM   #307
borges is offline borges  Norway
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Hi Alex,

I thought it would be sufficient to recycle the LRCK an SCLK from the DAC channel.

I2S was never fun to implement on a sequential processor....

BÝrge
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Old 29th October 2011, 12:33 AM   #308
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Using the DAC i2s clocks for the ADC is a possibility which we have not explored. Will need detailed study and experimentation to see how the clock signals behave wrt timing.

Alex
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Old 29th October 2011, 06:11 AM   #309
borges is offline borges  Norway
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Hi Alex,

According to section C.5.10 I2S of http://www.cyantechnology.com/public...0Manual-33.htm
both outgoing and ingoing serial data are sampled by a positive bit clock edge. So for test purposes it should be possible to selectively patch DAC serial output to ADC serial input. (Add a pull-down to ADC in so that it returns 0 when patch is not present.)

Do you think it is feasible that outgoing serial data is updated at negative edge while incoming serial data is read on the following positive edge?

BÝrge

Last edited by borges; 29th October 2011 at 06:17 AM.
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Old 29th October 2011, 06:28 PM   #310
borges is offline borges  Norway
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Special offer for analog modders: Do blind testing with two kits. Buy two units and I throw in the shipping. Normal kits feature 5 OS-CONs assembled at critical loads. The two-kit analog modder's package comes with 10 loose OS-CONs for your soldering joy :-)

BÝrge
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