As to whether you get a clock from an idle link, with the chips I've used, yes. Many years ago it was the YM3623B and more recently a DIR9001. With my DIR the idle clock frequency is considerably lower than 44k1 though.
<edit> A digital PLL with CPLDs is still a PLL. If you're doing feedback from the phase (buffer fullness), then its a PLL.
<edit> A digital PLL with CPLDs is still a PLL. If you're doing feedback from the phase (buffer fullness), then its a PLL.
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