Building a proper input & oversampler (i.e. front-end) for PCM1704

[abraxalito]

Well if you really believe that a 1s buffer is needed to have an effect on 1Hz jitter, go ahead and market such a solution. I predict that you'll be undercut by people doing it with much smaller buffers...

[Ken Newton]

Originally Posted by SoNic_real_one

Where did you find that info about the "FIFO" buffer in WM8804? I cannot find it in the datasheet.

BTW: The buffer is necessary for a complete low-freq jitter elimination. If you want to go down to 1Hz you need to store at least 1 second worth of data - how many bits are in 1 second? 44.1x1000x2x16=1411200=1378kbits=1.3Mbits. That's the minimum buffer you need!

Wolfson refers to it as an "Elastic Buffer", the functioning of which is described in the below linked 2006 AES paper presenting a new S/PDIF reciever architecture. That paper, which can be found on the Wolfson website under "white papers", undoubtedly descibes the general architecture of both the WM8804 and WM8805. Therein, the Elastic Buffer is described as "essentially a buffer that has asynchronous read and write interfaces". To me, that is describing an asynchronous FIFO, which, along with a fractional-N numerically controlled oscillator, are core elements of a digital PLL. I've not taken the time to understand what Wolfson is doing with that sigma-delta modulator they've also got in there.

http://www.wolfsonmicro.com/document...r_Oct_2006.pdf

[Ken Newton]

Originally Posted by SoNic_real_one

That new (2009) CS2300 is an interesting cip... didn't see it before.
Down to 1Hz PLL filter sounds interesting. And it can take XTALL inputs too (I am thinking about cleaning some existing Xtal/PLL divider jitter).
As for DIR9001 - TI claims 50ps recovered jitter. WM clamis for 8804 the same 50ps... I know that WM says that their part goes down to 100Hz and the "competitor" just to 10kHz... but I don't know if that is refering to TI part

Yes, the CS2300 does sound interesting. In fact, I've wondered why Cirrus hasn't yet integrated it with their CS8416. Seems a highly natural pairing which would more than compete with the Wolfson DIR chips.

[SoNic_real_one]

Originally Posted by Ken Newton

Wolfson refers to it as an "Elastic Buffer", the functioning of which is described in the below linked 2006 AES paper presenting a new S/PDIF reciever architecture. That paper, which can be found on the Wolfson website under "white papers", undoubtedly descibes the general architecture of both the WM8804 and WM8805.

No, it doesn't say clear that is/will be implemented...
I think they did implement the fractional PLL, but I didn't see any reference in the 8804/05 to the absolutelly necessary FIFO buffer described in the white paper.
Actually, they say "S/PDIF recovered clock using PLL, or stand alone crystal derived clock generation."
The device described in the white paper would be having the word and there.
Also in the datasheet they don't say nothing about a buffer. External clock it just "helping" the PLL loop, but the loop is still specified as beeing locked on the incoming signal.
The buffer would allow the asyncron functionality of the receiver, decoupling the input PLL loop from the XTALL generated output.

[Ken Newton]

Frankly, the thrust of your debate on this point eludes me.