Nice one!
I'd like to suggest using a voltage ref. instead of R16 (better PSRR on V-, higher output Z of the CCS, better control over the inputZ).
You may use also a little trick to isolate the filter from the load and avoid the re-entry due to the limited 'GBW' of a FET buffer. Here's a link
Okay, I still have to figure out how to post a link with the new software.
Again: http://www.diyhifi.org/forums/viewtopic.php?p=40436#p40436
I'd like to suggest using a voltage ref. instead of R16 (better PSRR on V-, higher output Z of the CCS, better control over the inputZ).
You may use also a little trick to isolate the filter from the load and avoid the re-entry due to the limited 'GBW' of a FET buffer. Here's a link
HTML:
http://www.diyhifi.org/forums/viewtopic.php?p=40436#p40436Okay, I still have to figure out how to post a link with the new software.
Again: http://www.diyhifi.org/forums/viewtopic.php?p=40436#p40436
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Nice trick with the decoupled FET as output buffer. PSRR isn't so bad as the current mirror output cancels voltage variations in the power supply. As I've posted this i/v stage in another thread first, I got some suggestions about the noise of the current sources. This is correct, the emitter resistors in the old version are quite low so this stage has a lot of noise gain.
In the second version I've tried to optimize the noise contribution. I was also able to simplify the circuit as well as improve the PSRR. Noise is mainly generated by R1, R2, R19 and R20. Nevertheless the output noise isn't outstanding low, I've calculated about 25nV/sqrtHz. When connecting the i/v converter to the ad1853 the SNR is lowered at about 3dB.
In the second version I've tried to optimize the noise contribution. I was also able to simplify the circuit as well as improve the PSRR. Noise is mainly generated by R1, R2, R19 and R20. Nevertheless the output noise isn't outstanding low, I've calculated about 25nV/sqrtHz. When connecting the i/v converter to the ad1853 the SNR is lowered at about 3dB.
Hi Bocka,
nice that you could improve the noise. What are the bias currents used in the 1st and 2nd stage? What is the voltage on the Vref input? If Vref is referred to ground, there is a direct low impedance path through the LED's, R9 and T7 from supply to ground, reducing the PSRR. Maybe you can further improve the PSRR by using a FET current source i.s.o. R9.
nice that you could improve the noise. What are the bias currents used in the 1st and 2nd stage? What is the voltage on the Vref input? If Vref is referred to ground, there is a direct low impedance path through the LED's, R9 and T7 from supply to ground, reducing the PSRR. Maybe you can further improve the PSRR by using a FET current source i.s.o. R9.
Hi jeepee,
the current through T8/T9 is about 4.5 ma. This will result in an input impedance of 10ohms for I+ and I-. The current through R1/R2 is about (3*1.8V - 0.7V)/470ohnm = 10ma. Idle current through T5/T6 is 10ma - 4.5ma = 5.5ma.
The AD1853 datasheet states Vref is about 2.7V but this voltage is not critical. Any voltage between 0 and 5V is O.K. The voltage on I+ and I- is exactely Vref.
The PSRR can estimated as follows:
Assuming R19 and R20 have 1% tolerance and the beta of all transistors is infinitive. So the current mirror (T13/T14) with the folded cascode has a PSRR of about 34dB. For the negative power supply an voltage changes are amplified by G = R14 / (R17 // R18) = 0.76 = -2dB. So we should get a PSRR- of about 36dB.
R9 sets the current through the LEDs at about 10ma. At 10ma the differential resistance of an ideal diode is about 4ohms. As we've got 3 LEDs in series the differential resistance of the 3 LEDs is 12ohms, maybe somewhat higher as the bulk resistance of LEDs is the same order.
For the positive supply voltage fluctuations are amplified by 12ohms * (1k + 12ohms) = 0.012 (-38dB). On the output we will see some additional gain as this voltage is amplified by R14 / (R1 // R2) = 7.65 (18dB). In this way PSRR- = 34dB + 38dB - 18dB = 54dB.
PSRR+ can improved by using a jfet current source. But as PSRR+ is about 20dB higher than PSRR- I think it's not worth it. A tighter tolerance of R19 and R20 will also improve PSRR- and costs nearly nothing (either matching resistors or use parts with 0.1% tolerance).
I've calculated an effective output voltage noise of about 3.5uV (@20kHz Bandwidth). As the PS shall not degrade the output significantly power supply noise must remain well below 100uV.
Although a simulation should give better results the calculations above should give a rough estimation.
the current through T8/T9 is about 4.5 ma. This will result in an input impedance of 10ohms for I+ and I-. The current through R1/R2 is about (3*1.8V - 0.7V)/470ohnm = 10ma. Idle current through T5/T6 is 10ma - 4.5ma = 5.5ma.
The AD1853 datasheet states Vref is about 2.7V but this voltage is not critical. Any voltage between 0 and 5V is O.K. The voltage on I+ and I- is exactely Vref.
The PSRR can estimated as follows:
Assuming R19 and R20 have 1% tolerance and the beta of all transistors is infinitive. So the current mirror (T13/T14) with the folded cascode has a PSRR of about 34dB. For the negative power supply an voltage changes are amplified by G = R14 / (R17 // R18) = 0.76 = -2dB. So we should get a PSRR- of about 36dB.
R9 sets the current through the LEDs at about 10ma. At 10ma the differential resistance of an ideal diode is about 4ohms. As we've got 3 LEDs in series the differential resistance of the 3 LEDs is 12ohms, maybe somewhat higher as the bulk resistance of LEDs is the same order.
For the positive supply voltage fluctuations are amplified by 12ohms * (1k + 12ohms) = 0.012 (-38dB). On the output we will see some additional gain as this voltage is amplified by R14 / (R1 // R2) = 7.65 (18dB). In this way PSRR- = 34dB + 38dB - 18dB = 54dB.
PSRR+ can improved by using a jfet current source. But as PSRR+ is about 20dB higher than PSRR- I think it's not worth it. A tighter tolerance of R19 and R20 will also improve PSRR- and costs nearly nothing (either matching resistors or use parts with 0.1% tolerance).
I've calculated an effective output voltage noise of about 3.5uV (@20kHz Bandwidth). As the PS shall not degrade the output significantly power supply noise must remain well below 100uV.
Although a simulation should give better results the calculations above should give a rough estimation.
Hi Bocka,
thanks for the values. In the mean time I've regenerated the circuit in the simulator and did some sims. Your PSRR calculations are very impressive. If I apply the 1% mismatch you assume, I simulate PSRR+ = 54.1dB, PSRR- = 40.01dB. "ich zieh den Hut", well done
. Circuit is nice and compact, I like that.
I'm still struggling with the output buffer though. I get a lot of distortion at >2V swing. What's your intended peak output voltage, or in other words, what the max output current from the DAC?
EDIT: okay my load resistace was too low @32 Ohm (Headphone). What's your target load resistance? >1kOhm?
thanks for the values. In the mean time I've regenerated the circuit in the simulator and did some sims. Your PSRR calculations are very impressive. If I apply the 1% mismatch you assume, I simulate PSRR+ = 54.1dB, PSRR- = 40.01dB. "ich zieh den Hut", well done
. Circuit is nice and compact, I like that.I'm still struggling with the output buffer though. I get a lot of distortion at >2V swing. What's your intended peak output voltage, or in other words, what the max output current from the DAC?
EDIT: okay my load resistace was too low @32 Ohm (Headphone). What's your target load resistance? >1kOhm?
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Hi jeepee,
thanks for your simulation. It's interesting that the PSRR simulation behaves nearly the same like my simple calculations.
The AD1853 has a differential output current of 3ma, pkpk so I can get a max. output voltage of 5.4 volts, pkpk = 1.9V rms. Erno Borbely did some real measurements for the jfet voltage follower (although some source degeneratin resistance is added). His article you can find here.
My target output impedance is something like 10k (preamp input). 32ohms is too low for a simple jfet follower, but maybe it can be done with a MOSFET. Mr. Borbely measures 0.0022% for a 10k load and 0.17% for 1k load and 3volts rms. I did also some simulation for that i/v converter and got a distortion level of -93dB for the largest harmonic at 10k load. This equates to 0.0022%, the same value Mr. Borbely measures.
For 1k load I got 0.046% in the simulation. This is somewhat lower but as the output voltage for the i/v converter is only 1.9V rms the simulation is in a very good agreement to Mr. Borbelys measurement.
I did also some AC analysis in a frequency sweep. VDB(17) is the "strange" output behaviour of T1 as the output impedance is not zero. The decoupled output T2 VDB(16) as sidiy suggested has got a 20dB better out-of-band suppression above some mhz, although the slope shows some irregularities.
thanks for your simulation. It's interesting that the PSRR simulation behaves nearly the same like my simple calculations.
The AD1853 has a differential output current of 3ma, pkpk so I can get a max. output voltage of 5.4 volts, pkpk = 1.9V rms. Erno Borbely did some real measurements for the jfet voltage follower (although some source degeneratin resistance is added). His article you can find here.
My target output impedance is something like 10k (preamp input). 32ohms is too low for a simple jfet follower, but maybe it can be done with a MOSFET. Mr. Borbely measures 0.0022% for a 10k load and 0.17% for 1k load and 3volts rms. I did also some simulation for that i/v converter and got a distortion level of -93dB for the largest harmonic at 10k load. This equates to 0.0022%, the same value Mr. Borbely measures.
For 1k load I got 0.046% in the simulation. This is somewhat lower but as the output voltage for the i/v converter is only 1.9V rms the simulation is in a very good agreement to Mr. Borbelys measurement.
I did also some AC analysis in a frequency sweep. VDB(17) is the "strange" output behaviour of T1 as the output impedance is not zero. The decoupled output T2 VDB(16) as sidiy suggested has got a 20dB better out-of-band suppression above some mhz, although the slope shows some irregularities.
Yes, I know. In my simulation file attachment (iv.cir) you can see I modeled the AD1853 outputs as 1ma dc current source with a +/- 0.75ma ac source. As long as T8/T9 are not reverse biased (this will happen at about 4ma) the converter stage should work fine. AFAIK nearly every new DAC chip has an output offset current today.
I'm not sure that we understand each other.
I try to say that outputs od AD1853 are not current source, but sink. It will not output any current but 'eat' current.If you connect resistor to output and ground there will be no sinal at all. You should use pull up resistor (which will be already I/V resistor too) to Vref (note that Vref pin od AD1865 cannot be loaded) or Vcc.
Forgive me If I didn't understand you correctly.
Regards
Marek
I try to say that outputs od AD1853 are not current source, but sink. It will not output any current but 'eat' current.If you connect resistor to output and ground there will be no sinal at all. You should use pull up resistor (which will be already I/V resistor too) to Vref (note that Vref pin od AD1865 cannot be loaded) or Vcc.
Forgive me If I didn't understand you correctly.
Regards
Marek
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Hi Marek,
yes I understood what you was trying to say. The first stage with T8/T9 is able to source and to sink about +/-4 ma into I+ and I-. As long the most positive and the most negative current is within this range, everything will work fine. But you're right, the current source in the netlist is modeled in the wrong way. In my understanding postive current is defined as current flows into a two-pole (in this way positive power will be dissipated), spice does it vice versa:
Positive current is assumed to flow from the positive node, through the source, to the negative node. A current source of positive value, will force current to flow out of the +node, through the source to the -node.
I've overlooked this (I simply used the values from the AD1853 datasheet). When I change the offset to -1ma there is not change in the output behaviour, so it's not worth to post the results. You can also build a complement type of the i/v converter (change NPN to PNP, PNP to NPN) and the circuit will work the same.
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I'm glad that you relise that. I was very confused when I tried to change my old OPAMP based output stage with passive one (tansformer). It was no signal and I didn't know why (datasheet seems to conceal this..)but when I exidently connected it not to ground but to Vcc - EUREKA! 
good luck with you project!
Marek
good luck with you project!
Marek
Hello again,
Running the buffers at Idss is not a really good way of doing the job. Using 'V' types with 22ohms source resistors will drive most typical loads at full swing while still in classA.
Of course using these gives higher outputZ (around 50ohm) and will change a bit the AC analysis posted earlier.
Running the buffers at Idss is not a really good way of doing the job. Using 'V' types with 22ohms source resistors will drive most typical loads at full swing while still in classA.
Of course using these gives higher outputZ (around 50ohm) and will change a bit the AC analysis posted earlier.
For the 2SK170 I dont think so (although I haven't tried this until now. I'll do this the next few days). dVgs = 200mV means more than worst case condition for the given IDss range. At 9mA a 2SK170 has a transconductance of about 40mS. For +/3ma current drain change will need about 40mS / 3ma = +/- 0.075V on Vgs. The same order can also read from the Vgs vs. Id graph from the datasheet.
Thermal mismatches are also minimised as the jfets run in single ended class a. For the servo the same problem are mismatches between the biasing resistors R17/R18, R1/R2 and R19/R20 will lead to the same order of imbalance on the conversion resistor. As the current through T6/T14 is about 5ma, only 1% imbalance results in 50ua * 1k8 = 90mv offset.
But you are right, the servo resistors R3/R4 are a little bit on the high side.
Hi Bocka,
I simmed a bit more on your circuit. I noticed quite some current through the diode string and the VREF transistor; (18V-2.7V-3*1.8V)/1k=10mA. What is the reason to use so much current on the biasing? I figured if you put 2 more LED's in the string, you can lower the base voltage of T5/T6 and increase the resistors R1/R2 (1k2) to lower the noise. I also increased the voltage drop accross R19/R20 (1k8) to further reduce noise. I got the noise down from 25nV/sqrtHz to 17nV/sqrtHz at the output node. Voltage headroom is still sufficient @ Idac_max. The 1st resistor in the Bessel filter is also quite high.
The noise contributed by the I2V resistor (1k8) was only 4.4% with your original values, now it is 10%. So there is still room for improvement ;-)
[R1/R2 & R19/R20 are still 50% of all noise]
I simmed a bit more on your circuit. I noticed quite some current through the diode string and the VREF transistor; (18V-2.7V-3*1.8V)/1k=10mA. What is the reason to use so much current on the biasing? I figured if you put 2 more LED's in the string, you can lower the base voltage of T5/T6 and increase the resistors R1/R2 (1k2) to lower the noise. I also increased the voltage drop accross R19/R20 (1k8) to further reduce noise. I got the noise down from 25nV/sqrtHz to 17nV/sqrtHz at the output node. Voltage headroom is still sufficient @ Idac_max. The 1st resistor in the Bessel filter is also quite high.
The noise contributed by the I2V resistor (1k8) was only 4.4% with your original values, now it is 10%. So there is still room for improvement ;-)
[R1/R2 & R19/R20 are still 50% of all noise]
Here are the distortion simulations from your original circuit with a 1kOhm and 10kOhm load. I swept the DAC current from 15uA to 1.5mA (=3mApp differential=AD1853 full scale current). As you already mentioned, 1kOhm is a but too much for the JFET buffer. The distortion on the output (node 'out') is an order of magnitude worse then on the JFET input (node 'mid'). 10kOhm load is fine though and quite comparable to the numbers you quoted.
The 2nd picture shows the harmonic composition of the distortion (left) and the trans-resistance; the harmonic transfer from input current to output voltage. Harm='1' is the 1k8 I-to-V resistor.
The 2nd picture shows the harmonic composition of the distortion (left) and the trans-resistance; the harmonic transfer from input current to output voltage. Harm='1' is the 1k8 I-to-V resistor.
LEDs are shining bright at that current...
There's not really an absolute value for that current. The higher the current, the lower the dynamic impedance for a diode is. As this diodes inject some noise I woudn't go for a to too small current. The optimum value is the current which also flows through T8/T9. When the NPNs and PNP have equal Vbe voltages the voltage on I+ and I- is the same as Vref. But I haven't calculated it. Just an ingenious value ;-)
I found the jfet buffer can drive a 5k load without any increase in distortion. If you want to drive a lower load this single jfet is not sufficiant.
The bessel filter is somewhat unconventional. The reason is I want to get the highest possible value for C1 as the nonlinear Cgd (about 6pF for each fet) is parallel to C1 and this leads to all kinds of distortion on higher amplitudes and frequencies. As I've got some problems to simulate the group delay in the past days I had to contact the software distributor first how to do it. They respond this morning and I simulated a nice 3us group delay so the calculated values are correct.
I think there are always some noise improvement possible. But as the noise figure is only 3dB I want to optimize the pcb first. The i/v converter is only a small part of the DAC, which has some hundred components
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