Discrete DAC i/v stage

[bocka]

I'm currently working on a new audio dac. As there is a lot discussion about discrete and chip i/v stages I've got another one here for the ad1853 with 75kHz bessel output filter. Redesigning for other dac chips could be done with little effort.

[sidiy]

Nice one!
I'd like to suggest using a voltage ref. instead of R16 (better PSRR on V-, higher output Z of the CCS, better control over the inputZ).
You may use also a little trick to isolate the filter from the load and avoid the re-entry due to the limited 'GBW' of a FET buffer. Here's a link

http://www.diyhifi.org/forums/viewtopic.php?p=40436#p40436

Okay, I still have to figure out how to post a link with the new software.
Again: http://www.diyhifi.org/forums/viewto...p=40436#p40436

[bocka]

Nice trick with the decoupled FET as output buffer. PSRR isn't so bad as the current mirror output cancels voltage variations in the power supply. As I've posted this i/v stage in another thread first, I got some suggestions about the noise of the current sources. This is correct, the emitter resistors in the old version are quite low so this stage has a lot of noise gain.

In the second version I've tried to optimize the noise contribution. I was also able to simplify the circuit as well as improve the PSRR. Noise is mainly generated by R1, R2, R19 and R20. Nevertheless the output noise isn't outstanding low, I've calculated about 25nV/sqrtHz. When connecting the i/v converter to the ad1853 the SNR is lowered at about 3dB.

[jeepee]

Hi Bocka,

nice that you could improve the noise. What are the bias currents used in the 1st and 2nd stage? What is the voltage on the Vref input? If Vref is referred to ground, there is a direct low impedance path through the LED's, R9 and T7 from supply to ground, reducing the PSRR. Maybe you can further improve the PSRR by using a FET current source i.s.o. R9.

[bocka]

Hi jeepee,

the current through T8/T9 is about 4.5 ma. This will result in an input impedance of 10ohms for I+ and I-. The current through R1/R2 is about (3*1.8V - 0.7V)/470ohnm = 10ma. Idle current through T5/T6 is 10ma - 4.5ma = 5.5ma.

The AD1853 datasheet states Vref is about 2.7V but this voltage is not critical. Any voltage between 0 and 5V is O.K. The voltage on I+ and I- is exactely Vref.

The PSRR can estimated as follows:

Assuming R19 and R20 have 1% tolerance and the beta of all transistors is infinitive. So the current mirror (T13/T14) with the folded cascode has a PSRR of about 34dB. For the negative power supply an voltage changes are amplified by G = R14 / (R17 // R18) = 0.76 = -2dB. So we should get a PSRR- of about 36dB.

R9 sets the current through the LEDs at about 10ma. At 10ma the differential resistance of an ideal diode is about 4ohms. As we've got 3 LEDs in series the differential resistance of the 3 LEDs is 12ohms, maybe somewhat higher as the bulk resistance of LEDs is the same order.

For the positive supply voltage fluctuations are amplified by 12ohms * (1k + 12ohms) = 0.012 (-38dB). On the output we will see some additional gain as this voltage is amplified by R14 / (R1 // R2) = 7.65 (18dB). In this way PSRR- = 34dB + 38dB - 18dB = 54dB.

PSRR+ can improved by using a jfet current source. But as PSRR+ is about 20dB higher than PSRR- I think it's not worth it. A tighter tolerance of R19 and R20 will also improve PSRR- and costs nearly nothing (either matching resistors or use parts with 0.1% tolerance).

I've calculated an effective output voltage noise of about 3.5uV (@20kHz Bandwidth). As the PS shall not degrade the output significantly power supply noise must remain well below 100uV.

Although a simulation should give better results the calculations above should give a rough estimation.

[jeepee]

Hi Bocka,

thanks for the values. In the mean time I've regenerated the circuit in the simulator and did some sims. Your PSRR calculations are very impressive. If I apply the 1% mismatch you assume, I simulate PSRR+ = 54.1dB, PSRR- = 40.01dB. "ich zieh den Hut", well done . Circuit is nice and compact, I like that.

I'm still struggling with the output buffer though. I get a lot of distortion at >2V swing. What's your intended peak output voltage, or in other words, what the max output current from the DAC?

EDIT: okay my load resistace was too low @32 Ohm (Headphone). What's your target load resistance? >1kOhm?

[bocka]

Hi jeepee,

thanks for your simulation. It's interesting that the PSRR simulation behaves nearly the same like my simple calculations.

The AD1853 has a differential output current of 3ma, pkpk so I can get a max. output voltage of 5.4 volts, pkpk = 1.9V rms. Erno Borbely did some real measurements for the jfet voltage follower (although some source degeneratin resistance is added). His article you can find here.

My target output impedance is something like 10k (preamp input). 32ohms is too low for a simple jfet follower, but maybe it can be done with a MOSFET. Mr. Borbely measures 0.0022% for a 10k load and 0.17% for 1k load and 3volts rms. I did also some simulation for that i/v converter and got a distortion level of -93dB for the largest harmonic at 10k load. This equates to 0.0022%, the same value Mr. Borbely measures.

For 1k load I got 0.046% in the simulation. This is somewhat lower but as the output voltage for the i/v converter is only 1.9V rms the simulation is in a very good agreement to Mr. Borbelys measurement.

I did also some AC analysis in a frequency sweep. VDB(17) is the "strange" output behaviour of T1 as the output impedance is not zero. The decoupled output T2 VDB(16) as sidiy suggested has got a 20dB better out-of-band suppression above some mhz, although the slope shows some irregularities.

[Marek]

Bocka,

you have to know than AD1853 isn't classical current-output DAC. it is like open-collector/open-drain output type!

[bocka]

Originally Posted by Marek

Bocka,

you have to know than AD1853 isn't classical current-output DAC. it is like open-collector/open-drain output type!

Yes, I know. In my simulation file attachment (iv.cir) you can see I modeled the AD1853 outputs as 1ma dc current source with a +/- 0.75ma ac source. As long as T8/T9 are not reverse biased (this will happen at about 4ma) the converter stage should work fine. AFAIK nearly every new DAC chip has an output offset current today.

[Marek]

I'm not sure that we understand each other.
I try to say that outputs od AD1853 are not current source, but sink. It will not output any current but 'eat' current.If you connect resistor to output and ground there will be no sinal at all. You should use pull up resistor (which will be already I/V resistor too) to Vref (note that Vref pin od AD1865 cannot be loaded) or Vcc.

Forgive me If I didn't understand you correctly.

Regards
Marek