SPDIF Re-clocking

[Ardee]

I am having trouble understanding how re-clocking data using a D type chip works.

The data is clocked to the rising edge of the master clock, which is fine if the data edge is always slightly behind the master clock edge. What happens though when a slightly jittery data edge corresponds with the clock edge? If the data edge is slightly behind the clock at one moment and slightly after it the next, will this not cause jitter of one clock period to be imposed on the data?

[alexcp]

That's possible, but unless the re-clocking clock frequency is an exact multiple of the datastream frequency, the probability of this happening should be low. You just get a slightly delayed but jitter-free copy of the original signal by resampling it with the (jitter-free) clock.

[SoNic_real_one]

It is gonna happen eventually, no matter what. D type cannot eliminate the jitter by itself.
SPDIF it will "loose" samples with a separate clock if you don't use a buffer to compensate de differences in frequencies.
Anyway, can you post a schematics of what are you talking about so we are on the same page?

[Ardee]

The kind of thing I am querying is here:

SPDIF Reclocking [English]

The only way I can see of doing this properly is to use a buffer and a synchronised source but no samples will be lost, as the master clock is running considerably faster than the incoming data rate.

[SoNic_real_one]

Yep, that's not gonna work as described.
I would completelly recreate the CD-player (transport) clock signals from the external DAC clock.