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-   -   I2S ground noise issues & possible resolutions (http://www.diyaudio.com/forums/digital-source/161924-i2s-ground-noise-issues-possible-resolutions.html)

jkeny 23rd February 2010 11:25 AM

I2S ground noise issues & possible resolutions
 
2 Attachment(s)
This is hived off from a thread about M2Tech HiFace 24/192 USB transport.

I have noticed a slight sharp edge to the sound of my modded HiFace set-up when using I2S as compared to SPDIF.

My I2S lines a short (1") & I'll work on improving them but I've been thinking that one explanation for this might be the SPDIF transformer providing galvanic isolation from the DAC. So I'm back to this old chestnut again of galvanic isolation.

Here's my summary of the info posted on this in that thread so far:
- high-speed USB 2.0(480Mbps) cannot be so isolated with currently available technology.
- isolating I2S will introduce jitter (using ADUM, etc)
- this could be an acceptable trade-off - Jitter Vs ground Noise
- if MCLK is rec-clocked after the I2S isolation it might be more acceptable.

One further thought occurred to me - what about splitting the I2S signal & going differential to two DACs i.e one DAC process R+/- & the other processing L+/-.

Would this achieve the same result as galvanic isolation in that it would remove common noise? I don't suppose the simpler version of one DAC processing R+/L+ & the other processing R-/L- would remove common noise (as effectively or at all?).

Can it be done effectively at 24/192 speeds?

Has anybody got any experience in using i2S balanced?

There is a Pedja Rogic PDF attached which shows how to split I2S for R+/- & L+/- use but it uses a discontinued chip (4517) & it is directed towards 16/44 operation

Lorien 24th February 2010 05:46 PM

Hello Jkeny,
I've also encountered this problem regarding transporting I2S signals but now I find a trade-off sollution which (from theory) it must work: try transporting I2S using LVDS. I've choosed few chips maded by TI but any other LVDS manufacturer should provide good parts (like National Semiconductors, Fairchild, On Semiconductors, etc).
The chip I've choosed to receive/"decode" LVDS signals is SN65LVDS2 in SOT23-5 (not mandatory :). Of course, I could choose a chip with 4 receivers on the same die but in my mind I thought that it could be better to have a separate PSU track for every LVDS receiver.
I hope it help you,
L

jkeny 25th February 2010 12:12 AM

I was looking to go with balanced I2S anyway, so I'm wondering would differential line drivers/receivers do the job DS8921/22 for instance. Would these be fast enough, low jitter? I know ECDesigns has used them in his I2S synchronous re-clocker but this was for 16/44 - I'm looking at 24/192 signals.

abraxalito 25th February 2010 02:04 AM

Quote:

Originally Posted by jkeny (Post 2095761)

Can it be done effectively at 24/192 speeds?

Has anybody got any experience in using i2S balanced?

There is a Pedja Rogic PDF attached which shows how to split I2S for R+/- & L+/- use but it uses a discontinued chip (4517) & it is directed towards 16/44 operation

Thanks for sharing that schematic, its helping me with a design I'm currently thinking about:D

The HEF4517 is still in full production according to NXP, however from the datasheet that circuit isn't guaranteed to work, though typically it will. It could never be made to work at 192kHz since that requires a bit clock frequency over 10MHz. Increasing the supply to the 4517 to 15V might do the trick though, then level shifters will be needed...

In any case I don't at the moment see how this circuit might take the place of galvanic isolation. If you've got ground currents, once they've been translated into noise at the bit-clock receiver, there's no way to undo the damage. That's because the generated error from the jitter is data-related - a jitter error when you've got digital silence is a different matter from a jitter error at full scale.

I'm currently investigating isolation schemes for my own project so will post something when I've got it to offer... As a first attempt, I think jitter only matters on the bit clock, not the other signals. So we only need to pay attention to that signal - others can have major jitter without any audible effects.

abraxalito 25th February 2010 02:27 AM

Low jitter clock receivers
 
Quote:

Originally Posted by jkeny (Post 2097955)
I was looking to go with balanced I2S anyway, so I'm wondering would differential line drivers/receivers do the job DS8921/22 for instance. Would these be fast enough, low jitter? I know ECDesigns has used them in his I2S synchronous re-clocker but this was for 16/44 - I'm looking at 24/192 signals.

Those parts look to have been designed for the old-style hard disks - I'm just about old enough to remember ST506 interfaces:cool:

Although they're fast enough, I'd not use them as their skew figures give some indication of the inherent jitter - worst case 2.75nS for the A variant. They're over-specified on common mode input voltage range, being usable on RS422 lines.

LVDS solutions I think would be a better choice. Have a look at DS90LV028AQ (receiver) and DS90LV027AQ (transmitter) instead.

jkeny 25th February 2010 08:08 AM

Quote:

Originally Posted by abraxalito (Post 2098114)
Those parts look to have been designed for the old-style hard disks - I'm just about old enough to remember ST506 interfaces:cool:

Although they're fast enough, I'd not use them as their skew figures give some indication of the inherent jitter - worst case 2.75nS for the A variant. They're over-specified on common mode input voltage range, being usable on RS422 lines.

LVDS solutions I think would be a better choice. Have a look at DS90LV028AQ (receiver) and DS90LV027AQ (transmitter) instead.

LVDS is a better spec but I also wanted to try achieve a R+/- & L+/- I2S signal stream as I'm thinking of using two DACs for balanced operation. It seems crazy to go SE to BAL & BAL back to SE for the LVDS process & then have to convert SE to BAL again! Any ideas?

analog_sa 25th February 2010 08:31 AM

Quote:

Originally Posted by jkeny (Post 2095761)
I have noticed a slight sharp edge to the sound of my modded HiFace set-up when using I2S as compared to SPDIF.


I would rather test the premiss that the "slight sharp edge " is indeed due to ground noise before jumping off the deep end of USB/I2S isolation. Not that it isn't worhtwhile. Only the cure may end up being worse than the ailment.

jkeny 25th February 2010 09:35 AM

Quote:

Originally Posted by analog_sa (Post 2098387)
I would rather test the premiss that the "slight sharp edge " is indeed due to ground noise before jumping off the deep end of USB/I2S isolation. Not that it isn't worhtwhile. Only the cure may end up being worse than the ailment.

I agree, it is a premise, based on the differnce I percieved in sound between SPDIF & I2S into the same Buffalo DAC. I know there are a lot of other parameters & differences that come into play here but I've tried it on a number of other DACs also & the same general difference in sound applies - SPDIF has a silky smooth sound with a good depth to the sound-stage; I2S has a more edgy & forward sound with less depth to the sound-stage.

The question really is - is I2S signal integrity or ground noise the cause of this ? I have a 100MHz scope but lack the competence in using it to verify signal integrity.

I have taken out the original 1" of wiring & replaced it with about 3" of individual twisted pairs for BCK,LRCK & DATA with some separation between them. I haven't connected it back together yet to listen & won't be able to for a while.

I guess one way of teasing out the issue would be to bypass the SPDIF output transformer by using instead a resistive divider for 75ohm impedance on the output of the DIT4192 SPDIF generating chip. This experiment will have to wait a while though.

abraxalito 25th February 2010 02:24 PM

Quote:

Originally Posted by jkeny (Post 2098372)
LVDS is a better spec but I also wanted to try achieve a R+/- & L+/- I2S signal stream as I'm thinking of using two DACs for balanced operation. It seems crazy to go SE to BAL & BAL back to SE for the LVDueS process & then have to convert SE to BAL again! Any ideas?

I'm not really sure from this what you're trying to achieve. Do you mean you want to send normal data from I2S into one DAC, and inverted data into another? If so, that will maybe improve SNR by 3dB and cancel out any 2nd order distortion components in the DACs. Such a differential configuration is easily implemented together with the LVDS balancing - to generate + and - data just choose the receivers without the termination resistors (-A rather than -AQ suffix) and correct them with opposite polarities, remembering to add an external termination. The step from SE to BAL (or back again) in digital is quite a lot simpler than in analog - just one of those LVDS chips does the trick. Since the DACs don't have BAL inputs, the conversion from BAL to SE is inevitable.

abraxalito 25th February 2010 02:32 PM

Quote:

Originally Posted by analog_sa (Post 2098387)
I would rather test the premiss that the "slight sharp edge " is indeed due to ground noise before jumping off the deep end of USB/I2S isolation. Not that it isn't worhtwhile. Only the cure may end up being worse than the ailment.

I'm wondering what full galvanic isolation might achieve, given that the DAC is going straight into headphones in this case- i.e. not into any other equipment with a ground referenced connection. If the DAC was being fed into a preamp, then on to a power amp it may well be justified. Another thing to try which is way, way simpler is to feed the cables between the computer and DAC through a series of ferrites to absorb RF hash wanting to travel out from the USB port. A few of the clip-on kinds of ferrites will certainly clean things up if applied at right next to the USB port.


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