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Old 2nd January 2013, 12:41 AM   #561
Bunpei is offline Bunpei  Japan
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Quote:
Originally Posted by Greg Stewart View Post
Any word on when Tachyon might produce another run of the SDTrans384?
I asked them their plan for the next release.
They are preparing it and hopefully going to start it by the end of this month.

Please send your reservation and estimate request to Tachyon.
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Old 2nd January 2013, 06:36 AM   #562
alanvcd is offline alanvcd  Hong Kong
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Dear Bunpei, once the new DAC option is available, pls remember to give us some hint.

Happy New Year to you !
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Old 9th January 2013, 07:25 PM   #563
jrling is offline jrling  United Kingdom
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Originally Posted by Bunpei
Please post your requesting messages here if you are interested in his DAC that is closely integrated with his SDTrans384.


I am interested thanks.
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Old 25th January 2013, 10:56 AM   #564
roender is offline roender  Romania
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Hi Bunpei,

May I ask you, please, how much delay would we expect to be introduced by SDtrans384 between MCLK and BCLK, MCLK taken directly from XCO and BCLK from CN8 pin header?

Thanks,
Mihai
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Old 26th January 2013, 05:09 AM   #565
Bunpei is offline Bunpei  Japan
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Hi, Mihai!

I asked Chiaki the delay. He has never measured it and me neither.
As only a simply divider circuit is implemented in the FPGA, the delay must not be so large.
I will measure it by a scope in a few days.

Bunpei
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Old 26th January 2013, 08:05 AM   #566
roender is offline roender  Romania
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Quote:
Originally Posted by Bunpei View Post
Hi, Mihai!

I asked Chiaki the delay. He has never measured it and me neither.
As only a simply divider circuit is implemented in the FPGA, the delay must not be so large.
I will measure it by a scope in a few days.

Bunpei
From your answer may presume that the final FPGA stage consists in three flip-flops with I2S signals as inputs and MCLK as reclocker signal?
If this is the case then delay is under 5nS
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Old 27th January 2013, 02:53 PM   #567
Bunpei is offline Bunpei  Japan
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Hi, Mihai!

I'm sorry that my previous answer was too simplified.

Precisely speaking, a rising edge of MCLK is a start point of series of digital processing.
After a certain delay resulted from FIFO-out processing, a first bit data appears. At the middle of the period of bit data assertion, a rising edge of the corresponding bit clock appears. Therefore, 1/ (64 x fs x 2) + alpha delay in all. However, the alpha is, approximately, a few ns, within the first half of MCLK period, namely, high level period.
So, it is not an "INVERTED MCLK" relation.

Would you observe the relationship with your oscilloscope in order to make it clear?

Bunpei
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Old 27th January 2013, 03:52 PM   #568
roender is offline roender  Romania
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Quote:
Originally Posted by Bunpei View Post
Hi, Mihai!

I'm sorry that my previous answer was too simplified.

Precisely speaking, a rising edge of MCLK is a start point of series of digital processing.
After a certain delay resulted from FIFO-out processing, a first bit data appears. At the middle of the period of bit data assertion, a rising edge of the corresponding bit clock appears. Therefore, 1/ (64 x fs x 2) + alpha delay in all. However, the alpha is, approximately, a few ns, within the first half of MCLK period, namely, high level period.
So, it is not an "INVERTED MCLK" relation.

Would you observe the relationship with your oscilloscope in order to make it clear?

Bunpei
Thank you for explanations.
I didn't expected inverted I2S signals at the output of the SD transport.
In fact, I believe that inverted MCLK is required in sync mode by the 9018 DAC for "nullifying" all the delays that are introduced by the I2S source.
In this case, the DAC will trigger I2S signal processing on the falling edge of the MCLK clock giving approx 1/2 MCLK time for the source to put all the data on the input of the DAC.
It doesn't maters if the DAC MCLK is inverted or the clock provided to the SDtrans is inverted (derived from the DAC clock), as the same logic will apply.

Last edited by roender; 27th January 2013 at 03:56 PM.
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Old 1st February 2013, 11:05 AM   #569
Bunpei is offline Bunpei  Japan
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A Japanese audio shop Tachyon is accepting an order for the second batch of SDTrans.
If you want to buy some, please contact to Mr. Yamasaki, an owner of the company.

jack<at>mtc<dot>biglobe<dot>ne<dot>jp

They say the number of the batch is 30 and a delivery is expected on February.
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Old 27th February 2013, 04:59 PM   #570
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Default SD Trans384 availability

Hi,
I just received shipping confirmation of my SD Trans from Tachyon. I hope to have it soon! Can anyone point to a great ps scematic to use with it?
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