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Old 21st October 2012, 11:56 PM   #531
Bunpei is online now Bunpei  Japan
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Dear Alan,

I appreciated your request very much.
As I am not directly involved in Chiaki's DAC project, I have not listened to its resulting sounds. Within a month or so, he will give me a chance. I will report his DAC here then.

His DAC board is announced to have the following features;
- ES9018 dual mono for stereo use
- Crystek 45.1584 and 49.152 MHz oscillators on board
- MCLKs are sent back to SDTrans so that I2S/DSD signals may be synchronous to DAC MCLKs
- No I/V module
- Five +5V independent power supply systems

He has not told me any release plan including a price yet.

Bunpei
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Old 22nd October 2012, 01:17 PM   #532
rolls is offline rolls  Switzerland
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Quote:
Originally Posted by Bunpei View Post

His DAC board is announced to have the following features;
- ES9018 dual mono for stereo use
- Crystek 45.1584 and 49.152 MHz oscillators on board
- MCLKs are sent back to SDTrans so that I2S/DSD signals may be synchronous to DAC MCLKs
- No I/V module
- Five +5V independent power supply systems

He has not told me any release plan including a price yet.

Bunpei
Hello Bunpei
I have often thought to go mono with ESS, but then you have 2 clocks that are not syncronous. Now I read that exactly this has been done: Your friend sends the 2 clocks back to the drive, and I2S is synchronous? Can you explain?
thank you
André
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Old 22nd October 2012, 01:40 PM   #533
Bunpei is online now Bunpei  Japan
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Quote:
Originally Posted by rolls View Post
... I have often thought to go mono with ESS, but then you have 2 clocks that are not syncronous. Now I read that exactly this has been done: Your friend sends the 2 clocks back to the drive, and I2S is synchronous? Can you explain? ...
Hi, André,

I'm afraid my summary of the features were not exact enough.
The transort, SDTrans requires both 44.1kHz x 512 and 48kHz x 512 master clock signals for fs of 44.1kHz series and 48kHz series.
That's why the DAC board has 45.1584 and 49.152 MHz oscillators. Output of one of these oscillators is enabled by selection logic signal from the transport side and the single output is forked into two ES9018 DACs.
One of selected output of oscillator is also sent back to the transport in order to generate I2S/DSD signals in synchronous manner in the transport.

I hope you can understand my explanation.

Bunpei
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Old 22nd October 2012, 02:29 PM   #534
roender is offline roender  Romania
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Quote:
Originally Posted by Bunpei View Post
Hi, André,

I'm afraid my summary of the features were not exact enough.
The transort, SDTrans requires both 44.1kHz x 512 and 48kHz x 512 master clock signals for fs of 44.1kHz series and 48kHz series.
That's why the DAC board has 45.1584 and 49.152 MHz oscillators. Output of one of these oscillators is enabled by selection logic signal from the transport side and the single output is forked into two ES9018 DACs.
One of selected output of oscillator is also sent back to the transport in order to generate I2S/DSD signals in synchronous manner in the transport.

I hope you can understand my explanation.

Bunpei

I had exactly the same idea, to use the highest possible CCHD-975 XOs in DAC, switched by request remotely from SDtrans :-) But there is a little problem here as not all DSD/PCM modes are supported by oversampling filter in Sabre DAC clocked under 50Mhz, so one must disable OSF for higher DSD/PCM mods.
Right now this is the only afordable solution ... or wait until Crystek make, if ever, 98.3040Mhz 90.3168Mhz versions of CCHD-957
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Old 22nd October 2012, 02:42 PM   #535
rolls is offline rolls  Switzerland
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Quote:
Originally Posted by Bunpei View Post
Hi, André,

I'm afraid my summary of the features were not exact enough.
The transort, SDTrans requires both 44.1kHz x 512 and 48kHz x 512 master clock signals for fs of 44.1kHz series and 48kHz series.
That's why the DAC board has 45.1584 and 49.152 MHz oscillators. Output of one of these oscillators is enabled by selection logic signal from the transport side and the single output is forked into two ES9018 DACs.
One of selected output of oscillator is also sent back to the transport in order to generate I2S/DSD signals in synchronous manner in the transport.

I hope you can understand my explanation.

Bunpei
I thank you for this detailed reply. I am interested, because I would like to slave my transport to the ESS Dac, and this is the same task.
There are not many people who have done it, and I am surprised to learn, that each of these clocks can drive both 2 dac chips and a sender chip.
I have seen in the data sheets, that the max load to the clocks is 15pF. You have a few cm to every chip, if it is located between the boards, and another few cm to the sender. I would be happy to see, that this works without loosing slightly of the fine qualities of these clocks. Then I hurry to buy a 25Mhz clock, suitable for my transport.
Thank you very much for your patience.
André
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Old 22nd October 2012, 02:51 PM   #536
roender is offline roender  Romania
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Quote:
Originally Posted by rolls View Post
Then I hurry to buy a 25Mhz clock, suitable for my transport.
André

It won't work with a 25Mhz XO.
In sync mode the internal ASRC in Sabre DAC will be automatically bypassed. In order to have sync connection between DAC and transport you must have MCLK as a multiple of fs.
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Old 22nd October 2012, 02:58 PM   #537
rolls is offline rolls  Switzerland
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Originally Posted by roender View Post
It won't work with a 25Mhz XO.
In sync mode the internal ASRC in Sabre DAC will be automatically bypassed. In order to have sync connection between DAC and transport you must have MCLK as a multiple of fs.
Somebody has clocked it very low in these pages, but I have yet to find it again.
Thank you.
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Old 22nd October 2012, 03:25 PM   #538
rolls is offline rolls  Switzerland
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Post 332 from Bunpei himself:

Quote:
Originally Posted by Bunpei View Post
Chiaki and Bunpei would like to recommend ES9018 DAC chip users try "synchronous master clocking" scheme on the chip.
In order to try this, the first thing you need to do is removing (temporarily) an original clock device on your DAC board.

The second step is to connect MCLK output pin of I2S connector of SDTrans to ES9018 XI pin.
There are two ways at this stage. The easier way is to provide 22.5792 or 24.576 MHz MCLK. In this case, you need to set "OSF =OFF" on ES9018 so as to maintain a stable lock on ES9018 from 44.1 to 384 kHz. You need neither EEPROM upgrade nor hardware jumper change. The users of SDTrans192 Rev. 2.1 can also try this.
I think I mean this post. They just slaved the DAC then and went to slave the drive later, which is better.
Bunpei, how do I set "OSF=OFF", when I need "neither EEPROM nor hardware jumper change"?
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Old 22nd October 2012, 11:43 PM   #539
Bunpei is online now Bunpei  Japan
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Quote:
Originally Posted by rolls View Post
... They just slaved the DAC then and went to slave the drive later, which is better.
Bunpei, how do I set "OSF=OFF", when I need "neither EEPROM nor hardware jumper change"? ...
Hi, roll,

What kind of transport and ES9018-based DAC do you have?
In the case of TPA Buffalo III DAC, you can set "OSF=OFF" by a simple DIP switch setting. In the other cases, you need a special mechanism for ES9018 register setting.
"Jumpering ..." and "EEPROM upgrade" are explanations for our transport "SDTrans384".

Bunpei
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Old 23rd October 2012, 10:52 PM   #540
rolls is offline rolls  Switzerland
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Originally Posted by Bunpei View Post
Hi, roll,

What kind of transport and ES9018-based DAC do you have?
In the case of TPA Buffalo III DAC, you can set "OSF=OFF" by a simple DIP switch setting. In the other cases, you need a special mechanism for ES9018 register setting.
"Jumpering ..." and "EEPROM upgrade" are explanations for our transport "SDTrans384".

Bunpei
Thank you for this explanation. I still use my "old" LipoFe driven 24bit TPA board, the drive is a Lampizator modified Denon 3910 with tube-SPdif output, which is really better than my beloved Teac P2s transport. I have the manual, it has a 24,576 Mhz quartz, but I assume, that my old chip will not work this way.
André
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