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Old 13th August 2012, 11:03 PM   #521
Bunpei is offline Bunpei  Japan
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Dear Patrick,

Nothing new on the idea, DSD+LPF.
This time, it revived in the context of DSD256 play where the increase of quantization noise occurs at four times higher frequency.

Bunpei
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Old 14th August 2012, 02:44 PM   #522
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May be that this buffer with some work, it'd be an interesting solution?


Joachim Gerhard Filter Buffer for ES9022

Ciao
Guglielmo
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Old 14th August 2012, 07:36 PM   #523
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Quote:
I also tried an "easy" LPF (LCR) directly connected to output pins of SDTrans384.
Which pins are these?
Is this exclusive to new version of SD Trans 384, or does my 192 V2.1 have the same connection? All I assumed was I2S type connections on mine.
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Never ending quest to get the noise out
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Old 15th August 2012, 11:25 PM   #524
Bunpei is offline Bunpei  Japan
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The upgrade to the DSD play supported version is available only for SDTrans192 board rev. 3.0 or higher.

Bunpei
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Old 21st August 2012, 09:38 PM   #525
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Hello Bunpei,
have you red this post:
Ian’s FIFO reclocker and Buffalo III DAC H i F i D U I N O

What do you think about the Si570 based clock board as low cost esternal board instead of your NDK oscillator board?
Ciao
Guglielmo
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Old 21st August 2012, 11:58 PM   #526
Bunpei is offline Bunpei  Japan
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Hi, Guglielmo,

Thank you very for the information. The device is very interesting for some aspects. I will tell Chiaki about this.
However, NDK is recently offering more reasonable prices and Si570 is also a rather expensive one. (Does anyone kindly tell me its actual price in a market?)

In principle, Chiaki and Bunpei used to have such a policy "avoid using PLL in a clock circuit as possible".

Bunpei
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Old 23rd August 2012, 12:18 AM   #527
Bunpei is offline Bunpei  Japan
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Default PCM to DSD256 conversion

Some SDTrans users may want to try a play of DSD256 sources. As DSD256 sources originally recorded on the rate are very rare, as a matter of fact, just one that I have ever listened to, we need to prepare them by converting existing PCM WAV files.
I'd like to recommend you use a program, WAV2DFF.exe, released by Sunacchi for that purpose. You can find some useful information DSD Playback system, DSF Player + USB DDC + DSD Amplifier
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Old 8th September 2012, 12:53 PM   #528
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As the SDTrans firmware may be using the conditional LSB extension routines I previously specified and requested for my own use I am now posting a warning here....

When music data in 16 bit two´s complement format is sent to devices with 24 or 32 bit depth the data must be LSB extended to the required bit depth.
This is also true for any music data like 24 bit as long as the source bit depth is lower than the destination bit depth.

The I2S «standard» states that 0 padding should be used for both positive and negative samples.
This method is creating an error for negative samples that varies with the inverse of the signal level-
For 0 dB FS (16 bit) (maximum level) the error is ca. 0.0035% and for a minimum signal level (1 bit signal) close to 100%.

It would have been more correct to conditionally LSB extend- «0» padding for positive samples and «1» for negative as this would have corrected the error for the negative samples,
but due to the ´two´s complement format error´ this conditional correction method will create its own errors..

This «combination effect» was discovered this when re-checking and re-calculating the conditional LSB extension method to provide updated data for the LSB extension white paper.

A proprietary method was invented that both allows for correct LSB extension and also correction of the ´two´s complement format error´- and is included directly into the discrete DAC128 state machine a DAC I now are finishing. This result in a output that is free of both the LSB extension error / distortion and the bipolar offset error normally created as a result of the ´two´s complement format error´, and also the "combination error" that will be created if corrections is not implemented correctly.

This solution was selected after extensive analysis of where and how the LSB extension errors and the ´two´s complement format error´ can / will occur and the effects it causes.

The bipolar offset caused by the ´two´s complement format error´ that causes a asymmetrical transfer function around bipolar zero have been addressed in many DAC designs - here a attachment showing how it was done in the PCM1702 DAC chips:


As a result of these findings the conditional LSB extension method as previously described should NOT be used directly without also implementing a correction of the ´two´s complement format error´...

Here is the simplest and gravest error the conditional LSB extension method will cause if used without the ´two´s complement format error´ correction routine:

The value -1 cannot be conditionally LSB extended due to the new value will still be -1.
Here shown with -1 and +1 to make it easy to "view":

A negative 16 bit value of -1:
1111111111111111 = -1
Extended "normally" to 32 bit:
11111111111111110000000000000000 = -65536
Extended "conditionally" to 32 bit:
11111111111111111111111111111111 = -1

A positive 16 bit value of 1:
0000000000000001 = 1
Extended "normally" to 32 bit:
00000000000000010000000000000000 = 65536
Extended "conditionally" to 32 bit:
00000000000000010000000000000000 = 65536

Regardless of what bit depth -1 is extended to the result will continue to be -1 with conditional extension...

More information regarding the combined "conditional LSB extension and the ´two´s complement format error´ routine" will be published when the white paper regarding this is finished.

In addition to the proprietary method (hardware) implemented and used for correct LSB extension and also correction of the ´two´s complement format error´- in the discrete DAC128 state machine in my DAC- I am also working on a software implementation that can be used together with other existing DAC chips.
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File Type: jpg BB PCM1702.jpg (93.6 KB, 508 views)
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Old 9th September 2012, 10:27 AM   #529
Bunpei is offline Bunpei  Japan
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Quote:
Originally Posted by RayCtech View Post
The I2S «standard» states that 0 padding should be used for both positive and negative samples.
This method is creating an error for negative samples that varies with the inverse of the signal level-
For 0 dB FS (16 bit) (maximum level) the error is ca. 0.0035% and for a minimum signal level (1 bit signal) close to 100%.
I can't understand at all the "error" you claimed.
Would you please show the error showing clear examples?
I think there is no error on the "0 padding".

To SDTrans users,

Please read the post I once wrote;

Quote:
Originally Posted by Bunpei View Post
SDTrans192 outputs I2S signal of BCLK frequency, 64*fs. This means formal bit length of one channel data is always 32 bit while effective bit length of actual data is 16, 24, or 32 bit depending on its sources. Therefore, in the case of 16 or 24 bit audio data, residual 16 or 8 bit space must be padded with dummy data.

As you may know, LPCM data in audio file is represented in a signed integer representation of 2's compliment.
Current FPGA program on SDTrans192 pads binary 0 for a positive value and binary 1 for a negative value. Originally, padding 0 for all values were adopted. One over seas user requested changing the method and we made the change because two users including the requesting person said "The new method brings better sonic effect."
However, the current way of padding, "binary 0 for positive value and binary 1 for negative value" is mathematically incorrect.

When we extend, for example, 24 bit signed integer to 32 bit signed integer, a method called "signed extension" should be used. In this operation, the sign of original integer is padded for "left side extended space"; binary 1 for a negative value and binary 0 for a positive value, respectively.
However, if we use this direct value for a play, dB value becomes small. Therefore, we should multiply 8 bit number. This requires "arithmetic left shift" that pads eight 0 to its right space. This operation is not sign dependent but involving only fixed 0.

I prefer a pragmatic approach. Even if the operation is "scientifically unsound", I agree with it as long as it results "better sounds".
One practical explanation supporting the "operation padding binary 0 for positive value and binary 1 for negative value" might be "possible favorable effects on power supply conditions for related digital circuits".
If any SDTrans384 users have questions on this point, please post your questions here. I will answer to you.

Bunpei
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Old 18th October 2012, 09:54 AM   #530
alanvcd is offline alanvcd  Hong Kong
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Dear Bunepi,

I've noticed that there is a new board of 9018D DAC with SDtrans together which looks very promising, could you introduce a bit of the latest development to us ?
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