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Old 26th March 2012, 03:06 PM   #431
Turbon is offline Turbon  Sweden
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Thanks for the update Bunpei. The price will naturally be in the vicinity of the combined price for the parts and PCB - right?
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Old 26th March 2012, 10:59 PM   #432
Bunpei is offline Bunpei  Japan
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Hi, Turnon,

Yes, your guess is correct. Chiaki and I are not doing this project for commercial business.
However, we selected the best or better components for audiophile and pursued high quality. As a result, our pricing may be considered as non-affordable for some people.

Bunpei
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Old 27th March 2012, 04:40 PM   #433
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Default Sync oscillators subboard option for ES9018 DAC

1. Introduction
Chiaki and Bunpei used to input I2S signals to ES9018-based DAC boards.
(ESS ES9018 Evaluation board, TPA Buffalo32s, TPA Buffalo II, TPA Buffalo III)
We found that achieving a lower DPLL bandwidth setting was very difficult for I2S input even if we used oscillators of low phase noise profiles on both the transport side and the ES9018 DAC side under an asynchronous master clock injection to the DAC chip.
Chiaki considered and inferred an internal mechanism of the DPLL adopted in ES9018 and came to the assumption that a quantization error in a time domain can't be ignored in the case of I2S input as long as an asynchronous master clocking scheme is used.
Then he decided to test "a synchronous master clocking method" using SDTrans384 and ESS ES9018 Evaluation board.
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Old 28th March 2012, 04:45 PM   #434
Bunpei is offline Bunpei  Japan
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Default Sync oscillators subboard option for ES9018 DAC

2. Generating synchronous master clock of 90.3168MHz/98.304MHz

SDTrans384 board has two low phase noise crystal oscillators of frequencies, 22.5792MHz and 24.576MHz made by NDK. At the first design of the board, raw output signals of these oscillators were directly connected to MCLK output pin. However, this signal had not been used for ES9018-based DAC.
As we had known that MCLK frequency higher than 90MHz is essential for playing 352.8kHz/24bit PCM(DXD) files without noises on OSF=ON mode, Chiaki added 4x multiplier DPLL circuit in FPGA. Then we have obtained an synchronous MCLK of 90.3168MHz/98.304MHz for output. In this context, "synchronous" means MCLK and other I2S signals, BCLK, LRCLK, SDAT are synchronous. The MCLK output is available on a standard SDTrans384 board kit that will be distributed in coming April.
Bunpei recognized a remarkable sonic improvement when he applied the synchronous MCLK of 90.3168MHz/98.304MHz to ES9018 chip on Buffalo II board for the first time. At the same time, this clocking scheme made us set "DPLL Bandwidth" parameter at "the lowest" even for I2S input and OSF=ON condition for 352.8kHz/24bit PCM.
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Old 29th March 2012, 03:17 PM   #435
Bunpei is offline Bunpei  Japan
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Default Sync oscillators subboard option for ES9018 DAC

3. Locating master clock oscillators on DAC board side

When Chiaki and Bunpei started this SDTrans project, we established one policy;
"Avoid using PLL in clocking"
Therefore, in the next step, Chiaki started a new design of locating 90.3168MHz/98.304MHz crystal oscillators on the DAC board side. In this configuration, the oscillator output signals are injected directly to ES9018 chip with the shortest wiring. At the same time, forked outputs are sent from the DAC side to the transport, SDTrans side and the master clock signals are divided by 4 so that it may be compatible to original NDK oscillators on board.
Here, we chosen NDK crystal oscillators of low phase noise profile of which frequencies are 90.3168MHz/98.304MHz based on a recommendation of the company. However, its unit price is 15,000 JPY = 180 USD! Moreover, its output signal level is LVPECL and we need a buffer in order to make compatible CMOS.
Beside that, Chiaki adopted such a switching mechanism for the two oscillators that a command sent from the SDTrans side depending on the sampling frequency of audio source files though I2C line controls a switching buffer located in the DAC side.
These features make the sub board to be attached on the DAC side very expensive.
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Old 29th March 2012, 03:27 PM   #436
Turbon is offline Turbon  Sweden
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Hmmm, affordable vs desirable...

I still feel that 2GB limit is very hard to swallow. Have you discussed to move to a more modern CPU with wastly larger address space? Something to accomodate a whole album at highest quality. Until then - this must remain as a dream - sorry.
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Old 29th March 2012, 03:43 PM   #437
CeeVee is offline CeeVee  Portugal
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Quote:
Originally Posted by Turbon View Post
Hmmm, affordable vs desirable...

I still feel that 2GB limit is very hard to swallow. Have you discussed to move to a more modern CPU with wastly larger address space? Something to accomodate a whole album at highest quality. Until then - this must remain as a dream - sorry.
Maximum size SD card is 32GB as per specs.
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Old 29th March 2012, 03:49 PM   #438
Turbon is offline Turbon  Sweden
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Quote:
Originally Posted by CeeVee View Post
Maximum size SD card is 32GB as per specs.
Hmmm, I missed that part somwhere and the discussion of the address space of the 8051... Bunpei, do you still want me as a customer if it handles 32GB's?

Brgds
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Old 29th March 2012, 06:08 PM   #439
Bunpei is offline Bunpei  Japan
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Quote:
Originally Posted by Turbon View Post
Hmmm, I missed that part somwhere and the discussion of the address space of the 8051... Bunpei, do you still want me as a customer if it handles 32GB's?
SDTrans384 handles a SDHC memory card, of which maximum volume size is 32GB and the maximum file size is 4GB. I'm afraid that you may think the max file size 4GB is not enough for a long classical music of DSD256 recording.

Chiaki does not use any direct address space of C8051 for processing audio data. The MCU is just used to issue read-out commands to the memory card. Its main task is to track FAT cluster chains.
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Old 30th March 2012, 10:47 PM   #440
Javin5 is offline Javin5  Switzerland
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Quote:
Originally Posted by Bunpei View Post
3. Locating master clock oscillators on DAC board side

When Chiaki and Bunpei started this SDTrans project, we established one policy;
"Avoid using PLL in clocking"
Therefore, in the next step, Chiaki started a new design of locating 90.3168MHz/98.304MHz crystal oscillators on the DAC board side. In this configuration, the oscillator output signals are injected directly to ES9018 chip with the shortest wiring. At the same time, forked outputs are sent from the DAC side to the transport, SDTrans side and the master clock signals are divided by 4 so that it may be compatible to original NDK oscillators on board.
Here, we chosen NDK crystal oscillators of low phase noise profile of which frequencies are 90.3168MHz/98.304MHz based on a recommendation of the company. However, its unit price is 15,000 JPY = 180 USD! Moreover, its output signal level is LVPECL and we need a buffer in order to make compatible CMOS.
Beside that, Chiaki adopted such a switching mechanism for the two oscillators that a command sent from the SDTrans side depending on the sampling frequency of audio source files though I2C line controls a switching buffer located in the DAC side.
These features make the sub board to be attached on the DAC side very expensive.
I think this is the only way if you want top, no-compromise quality. Yes, it is expensive, but you are shooting here for the top. Quality at this level has its price. Some people just don't want to realize that.
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