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Old 14th August 2011, 04:53 PM   #341
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Join Date: Nov 2004
Location: Udine
Hello Bunpei,
did you received my emil?
Ciao
Guglielmo
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Old 3rd September 2011, 08:24 PM   #342
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Default New Japanese IV transformers

Some of you might be interested in reading the mini review of a new IV transformer for the Buffalo2 I wrote today.

Buffalo II & transformers
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Old 8th September 2011, 01:53 PM   #343
Bunpei is offline Bunpei  Japan
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Default DPLL Bandwidth parameter "no bandwidth"

On his BBS, Chiaki reported his successful result of playing DXD 352.8 kHz /24 bit PCM files with ES9018 DAC chip by setting DPLL Bandwidth parameter "no bandwidth" under "OSF=ON" and "Jitter reduction=ON".

The key point is feeding a "synchronous master clock" generated in SDTrans384 to ES9018 DAC chip. The master clock frequency is 90.3168 MHz.
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Old 23rd September 2011, 03:58 PM   #344
Bunpei is offline Bunpei  Japan
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Default Connecting to TAS5706 Evaluation Board

I could connect TI TAS 5706 (full digital input Class-D amplifier) to SDTrans384 via I2S by setting some registers on the chip using Arduino.
The chip on its evaluation board could play PCM WAV files ranging from 44.1 kHz/16 bit to 192 kHz/24 bit without any problem.

DAC chips and full digital input Class-D Amplifier chips I have confirmed the compatibility of SDTrans are;
<DAC>
Wolfson Microelectronics: WM8741 ( - 192 kHz/24 bit)
ESS Technology: ES9018 ( - 352.8 kHz/24 bit)
Asahi Kasei Microdevices: AK 4399 ( - 352.8 kHz/24 bit)
Texas Instruments: PCM1794 ( - 192 kHz/24 bit)
<Class-D amplifier>
STMicroelectronics: STA328 ( - 192 kHz/24 bit)
Texas Instrumenents: TAS5706 ( - 192 kHz/24 bit)
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Old 8th October 2011, 03:05 PM   #345
elecon is offline elecon  Japan
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I am very spoilt :-D

This is because Bunpei personally works on my entire Buffalo 3 and SDTrans 384 playback system and visits my home in Setagaya, Tokyo frequently. It is of course a give-and-take, because both Bunpei and myself get to learn from the various experiments done.

The latest iteration is 2 x Buffalo 3 converter boards connected in parallel stereo with the exotic Urushi Painted "Feastrex Branded" line transformers. Bunpei has also programmed the ARDUINO controller for 9-bit quantizer operation of the ESS 9018s. Finally a pair of hefty OS Con electrolytic caps has been connected to the to the regulators. I understand that this is a risky proposition that is not recommended by the supplier, but I think that as long as I take the responsibility for any eventual damage myself, everything should be allowed in DIY audio bar causing fire or explosions :-D

The system does of course include the "synchronous master clocking" scheme and the Cornell Dubilier Electronics (CDE) film capacitors in the power supply. BTW: the SDTrans 384 itself is powered by three or four Panasonic Evolta D-Cells.

The previous iteration was based on a single Buffalo 2 which also had been set to 9-bit quantizer, but without any separate regulators or caps in the regulation. I can report that the sound improvement today was one of the biggest jumps upward that I have experienced in the Buffalo/SDTrans development. The sound is richer, creamier, higher resolution, more elegant, more vivid. It simply makes you feel like listening to more great music!

I normally use the excellent Fidelix Caprice, and I have not yet done a direct comparison. This isn't really about any "shoot-out" anyway. I look at the Buffalo development as one direction and the Caprice as another. I am quite happy that both can deliver satisfactory sound at their individual "vectors".

Last edited by elecon; 8th October 2011 at 03:31 PM. Reason: Added content for better understanding ;-)
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Old 18th October 2011, 09:23 PM   #346
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Hello Bunpei,

Does the FPGA add much jitter to the I2S output?

Cheers
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Old 19th October 2011, 09:36 AM   #347
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Default ES9018 "No Bandwidth" experience

A few month ago I tried No bandwidth setting with syncronous ES9018 clocking, just after seeing Chiaki's report on his BBS.
It seemed that ideal mclk frequency varies depends on samplelates.

MCLK frequencies I had succeeded to play music files - not perfectly, BII failed to lock every 30-40 seconds - under No Bandwidth setting are as follows.

Tested with Buffalo II dac (OSF on) - i2s - SDtrans384 with number17 EEPROM.


352.8khz - 90.3168mhz from mclk output
96khz - 24.576mhz, tapped from CN11
44.1khz - haven't succeeded with STtrans-BuffaloII combo, only succeeded when using QA-550 sd card transport and tapping 11.2896mhz XO from it.


I feel ES9018's master clock should be close to correct mclk requirements when aiming "No Bandwidth" DPLL setting under syncronous clocking scheme.

But honestly to say, I couldn't find obvious sonic improvement with changing DPLL setting from "Lowest" to "No Bandwidth".
Lowest or even higher DPLL is fine to me under syncronous clocking.

About "correct mclk requirements", forum member glt made great effort to gathering informations and well explains in his "Hifiduino" blog.
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Old 19th October 2011, 02:48 PM   #348
Bunpei is offline Bunpei  Japan
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Quote:
Originally Posted by mrbear View Post
Does the FPGA add much jitter to the I2S output?
Hi, mrbear,

It's a tough question.
In an objective way, there is no way to measure it properly for me.

On SDTrans384, I2S signals (LRCLK, SDAT, BCLK) are generated in FPGA based on an external clock. As for MCLK, we have two selections. One way is to use the original external clock as MCLK and another way is to derive MCLK from the FPGA. When I compared the subjective sonic impressions before, I felt the former way was better. However, at the experiment, my preparations for power lines were not adequate enough.

If you can explain your question more in detail, I may be able to give you more suitable answer.
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Old 20th October 2011, 04:14 PM   #349
Bunpei is offline Bunpei  Japan
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Quote:
Originally Posted by wktk_smile View Post
352.8khz - 90.3168mhz from mclk output
96khz - 24.576mhz, tapped from CN11
44.1khz - haven't succeeded with STtrans-BuffaloII combo, only succeeded when using QA-550 sd card transport and tapping 11.2896mhz XO from it.

I feel ES9018's master clock should be close to correct mclk requirements when aiming "No Bandwidth" DPLL setting under syncronous clocking scheme.
It's quite an interesting finding! I think we need to have more experiments on this point.
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Old 10th November 2011, 11:35 PM   #350
Nanook is offline Nanook  Canada
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Default perhaps a little off topic...

I have a SD card "music sampler" used in music stores. It uses an AVI amp with a SD card music "file" reader and speakers. The board is made by Somerset (I think). Digital readout for song number. I didn't get the face plate, so can't tell if there is a "next" button it. If any want I could take photos of it.
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