Stand-alone HDCD decoder project

[rossl]

This is my HDCD digital filter box.

first version

I used a little extruded case that I bought on eBay.
Hammond Mfg. 1455L1201BK

[rossl]

picture from the back

I'm using a little 4.5 watt wall wart power supply

first version

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PCB bottom picture

113 surface mount resistors on the PCB bottom side. All digital signals are impedance controlled, The circuit board is a 4 layer-board with a full ground plane inside on layer 2. The third layer is filled with five seperate planes for all the power supplies.

Flooded ground areas on the top and bottom.

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bare PCB picture

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PARTS




top picture



1. CS8416 SPDIF receiver with two coax inputs.

2. Altera EPM7064S.

3. JTAG port used to flash the Altera.

4. PMD100 HDCD chip.

5. Channel button.

6. Channel indicators

7. Scale button.

8. Scale, ERROR, HDCD, >48K indicators

9. 74ACT2229 dual FIFO.

10. PIC16F677 Controller.

11. Chassis Ground terminal for static protection.

12. CS8406 SPDIF transmitter and coax output.

13. 74AHCT157 mux.

14. Transformer isolated I/O.

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Theory of operation

The CS8416 SPDIF receiver with two coax inputs will receive up to 192K.

The Altera EPM7064S provides all the glue logic between receiver, PMD100, FIFO, and transmitter. The only exception is the master clock from the receiver goes to both Altera and transmitter with impedance controlled traces.

I bought the PMD100 HDCD chip on eBay and it was shipped in from Asia. I have it set to oversample 2X. Therefore, 44.1K data input becomes 88.2K data output.

The Scale button will manipulate pin 19 of the PMD100. I also provided jumpers in case I decide I don't need a scale button and want to leave it set a certain way.

The 74ACT2229 FIFO has two channels 512 bits deep. After the receiver locks on to a SPDIF stream, the FIFO will come out of reset and the PMD100 will begin to clock in sets of 24 bit data words into the FIFOs.

Once the FIFOs get half full, the Altera controller will begin to clock out and assemble a left-justified data stream for the transmitter.

The data gets clocked from PMD100 into the FIFO pair with 24 bit clocks, left and right at the same time. The data gets clocked out of the FIFOs with 24 clocks for the left, 8 zeros inserted, 24 clocks for the right, and 8 more zeros inserted. The FIFO stays approximately half full with about 10 or 11 samples rippling through at any time. The Altera generates an appropriate bit clock and word clock for the output data stream.

The PIC16F677 Controller resets the box and sets up the PMD100, and controls the front panel buttons and lights. She also holds in EEPROM a bit for the current channel and a SCALE bit for each channel. These 3 EEPROM bits will restore the box to prior settings at power on.

The 74AHCT157 mux bypasses the PMD100 when the received data stream is greater than 48K.

The CS8406 SPDIF transmitter uses the 256x received data clock. When the input data is 48K or less and the PMD100 is upsampling 2X, the CS8406 has HWCK0 set for 128X clock.

If the input data stream changes to above 48K, the processor sets the mux to bypass the PMD100, set the CS8406 HWCK0 to 256X clock, and give a quick reset to the CS8406 to make the change.

If the input data stream goes back to 48K or less, the processor sets the mux to the FIFO outputs, set the CS8406 HWCK0 back to 128X clock, and give a quick reset to clear the FIFO and CS8406 to make the change.

The processor also controls the PMD hard mute input in case the channel or scale button gets pushed, recieve lock is lost, or data input is >48K.

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second version. I built up the second PCB and soldered the HDCD chip in without using a socket.

22uF MLCC ceramic caps, 6V3 X7R, are soldered directly to the power pins. thanks to carlosfm for the tip to reduce the noise on the PMD-100.

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The second version has BNC connectors instead of RCA jacks.

(RG-187 courtesy of Jocko)

I also added 13000uF of capacitance to improve the hold-up time through power line glitches.

I am happy with the sound.

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I designed and ordered custom front panel and rear panel from frontpanelexpress.com

[philpoole]

Thanks for posting. Very well made.

I have a PMD100. But, ahem, its not exactly as well made. They sound great don't they?

Why are you only running at 2x? Surely you want to run it in 8x
If you're running off a wall wart, I guess you have the advantage of a seperate transformer, but do you find your regulation good enough? I see you have a lot of decoupling going on. I guess its enough due to the seperate power supply and the isolation SPDIF can give you.

I like the decoupling on the actual chip pins. Did you notice a difference after this was implemented?

Mine's only in stand alone mode. I'd quite like to implement a PIC to drive it one day.