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Old 27th February 2010, 01:59 AM   #501
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Default LVDS and jitter

Quote:
Originally Posted by RayCtech View Post
On the devices I have looked up the worst case timing was 0.5ns = 500ps.
Is this a jitter spec? In the DS90LT012A (National) datasheet, there's no jitter spec, merely a skew figure of 400pS max. Have you found a datasheet with a jitter figure?

Quote:
As the "Other" I wonder - do you go public with all your private conversations?
I think the 'other' here is me, on the thread jkeny has already referenced. I'm keen to use LVDS in my upcoming project, but only if its low enough in the jitter dept...

Last edited by abraxalito; 27th February 2010 at 02:04 AM. Reason: combined two responses into one post
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Old 27th February 2010, 07:52 PM   #502
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Hi jkeny,

Quote:
Thanks John,
I wondered if there is any advantage to this form of i2S split streams (pic attached) rather than to just inverting the I2S stream & sending it to an identical DAC for the R-/L- analogue side ?
Splitting I2S stream enables one DAC chip to process one channel only (L+ / L-) or ( R+ / R-). Inverting data only will create both channels in one chip (L+ / R+) or (L- / L-).

Split I2S may have advantage of better channel separation and matching / tracking of balanced outputs of each channel.
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Old 27th February 2010, 07:58 PM   #503
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Quote:
Originally Posted by -ecdesigns- View Post
Hi jkeny,



Splitting I2S stream enables one DAC chip to process one channel only (L+ / L-) or ( R+ / R-). Inverting data only will create both channels in one chip (L+ / R+) or (L- / L-).

Split I2S may have advantage of better channel separation and matching / tracking of balanced outputs of each channel.
Hardly seems worth the extra effort then - just using an inverter seems to get you most of the way there. I thought processing one channel L+ / L- in one DAC might give a better common mode noise & 2nd harmonic cancellation due to better matching but I wasn't sure how much better?
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Old 27th February 2010, 08:12 PM   #504
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Hi abraxalito,

Check Farnell, jitter specs are specified there (peak-to-peak jitter)

Some examples:

NATIONAL SEMICONDUCTOR|DS90LT012AHMF/NOPB|LVDS Line Receiver IC | Farnell Nederland
NATIONAL SEMICONDUCTOR|DS15BR400TVS/NOPB.|Buffer IC | Farnell Nederland

Differential LVDS chips:

DS90LT012AHMF/NOPB, 1500ps
DS90LV011ATMF/NOPB, 1200ps
DS90LV017ATM/NOPB, 1200ps
SN56LVDS32BDR, 1000ps
FIN1001M5X, 1000ps

The best I found so far:

DS15BR400TVS/NOPB (2Gbit / second), 31ps

Even this is not optimal, this is only jitter of one driver or one receiver, interlink induced jitter will also be added.

I am aiming at jitter specs over the frequency range of interest, that are way lower than this.
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Old 27th February 2010, 08:14 PM   #505
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Using +L/-L and +R/-R will cancel out (to a great deal, as both channels are not an exact match) the audio currents going through +5.

Using an inverter in I2S mode coding scheme is not perfect (discussed before on this forum to great lengths ).
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Old 27th February 2010, 09:11 PM   #506
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Quote:
Originally Posted by guido View Post
Using +L/-L and +R/-R will cancel out (to a great deal, as both channels are not an exact match) the audio currents going through +5.
Sorry, what's +5? Even though both channels in the DCA are not an exact match they are probably more closely matched than the channels across 2 DACS.

Quote:
Using an inverter in I2S mode coding scheme is not perfect (discussed before on this forum to great lengths ).
Sorry again, I searched but missed where this was discussed before - any link or synopsis why it's not perfect?

Also, would a picogate be the best solution for inverting I2S like this SN74LVC1GU04DBVR ?

Last edited by jkeny; 27th February 2010 at 09:16 PM.
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Old 27th February 2010, 09:21 PM   #507
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+5 is the power supply pin for 5V of the TDA

And an inverter not perfect, as the inverted signal is 1 bit of. And at one of the max values (can't remember pos of neg), the inverted signal is completely wrong. Look at the coding scheme (2's complement iirc) and what an inverter would do.
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Last edited by guido; 27th February 2010 at 09:26 PM.
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Old 27th February 2010, 09:40 PM   #508
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Quote:
Originally Posted by guido View Post
+5 is the power supply pin for 5V of the TDA
OK, I see but I'm talking more in general terms & not just TDA DACs

Quote:
And an inverter not perfect, as the inverted signal is 1 bit of. And at one of the max values (can't remember pos of neg), the inverted signal is completely wrong. Look at the coding scheme (2's complement iirc) and what an inverter would do.
Do Raytech's comments change this?
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Old 27th February 2010, 11:29 PM   #509
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Ok, i was thinking of the 1541 specifically.
As for the ES chip, depends on the coding used.
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Old 28th February 2010, 08:20 AM   #510
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Hi guido,

Quote:
And an inverter not perfect, as the inverted signal is 1 bit of. And at one of the max values (can't remember pos of neg), the inverted signal is completely wrong.
Imagine a 3 bit DAC, with symmetrical signal swing around "zero"

0, 1, 2, (3), 4, 5, 6 or 1, 2, 3, (4), 5, 6, 7

Two's complement:

Two's complement - Wikipedia.

Symetrical swing (two's complement) would be:

-3, -2, -1, 0, +1, +2, +3 or 101 (-3), 110 (-2), 111 (-1), 000 (0), 001 (+1), 010 (+2), 011 (+3)

100 (-4) is also a valid two's complement number, but isn't used here.


When DAC chip (16 bits) receives 0 (0V) all bit switches are OFF, representing minimum (zero) output current, the current could only increase now (couldn't go negative). In order to correct this, a bias current is introduced, equal to full scale current divided by 2 plus some margin to compensate for DC drift (risk of clipping at zero mA). Now we have say 2.01mA when all bits are off (0), 4.01 mA with +32767, and 0.01mA with -32767. We now effectively use 65535 of the possible 65536 values. The value -32768 remains unused.

Back to inverting data for generating inverted signal,

Inverting bits:

010 (+2), 001 (+1), 000 (0), 111 (-1), 110 (-2), 101 (-3), 100 (-4)

All values are now 1 bit off, zero now represents (-1), in this case resulting in a 1 bit negative DC offset (see example).

In order to correct this, invert data and add 1

Since -4 (-32768 with a 16 bit DAC) is still a valid number, it will be processed correctly by the DAC chip. It simply results in bit switch code 1000000000000000 meaning only MSB is switched on. The negative DC offset will be no problem because of bias current margin that is more than sufficient to compensate for 1 LSB drift / offset.

In short, when inverting data, all resulting values will be off one LSB, causing a 1LSB negative DC offset, the effects of a 1 LSB DC sift are debatable.
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