VRDS and I2S

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I would like to know if there is an I2S signal somewhere in a Teac VRDS-type transport? It would be great to forgo the SPDIF link and use a buffered I2S link to connect the transport to the DAC or just build the DAC inside the transport.

I'm using a Teac P700 transport at the moment, but I'm looking for a VRDS-T1 that has a lot more room in the box for modifications.
 
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inside a T1

I've got a T1 transport and I've got the schematic. I don't know enough about I2S to say if you can tap the needed signals, but for those with more expertise, here's a scan of part of the schematic where I think you should be able to pick up the signals. Can anyone else comment?
---Gary
 

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VRS and I2S

Hi PJR and Gary B,
I think that I help you in the model of GaryB I can see the eschematic of the pins U403 and I see the pins numbers
32 is LRCK, 34 is DATA, 35 SCLK all pins
connected with the resistor of 220 Ohms.
You can pick up next these resistors and you have the three singnals that we need for the I2S bus, I can help you more but I need the reference
of the U403, Type and manufacturer.

By carefully you don´t connetc before
the resistor becouse the square wave
is bettre next these resistors.


PJR if your Teac transpor use the same
chip the solution is the same.

Best Regards.

Jesús
 
CXD2500AQ

Hi gary,
I didn´t found the datasheet of the CXD2500AQ, I visited the web of sony semiconductors and I found that the CXD2500AQ is Discontinued Device :bawling:
But you don´t worry becouse I´m sure that you pick up in the lines that I explained at you and it is Ok.
I´ll go to found the data sheet.

Jesús Puerto.
 
By carefully you don´t connetc before the resistor becouse the square wave is bettre next these resistors.

really? the square wave looks nicer after the resistors? why would this be?

i connected them before the resistors because my digital decoder datasheet says these pins can only put out a maximum of 1ma. so if i could squeeze in an inch closer, i would do so.

http://diyparadise.com/rm20dac.html

DonJuan
 
GaryB and Jesús,

Thanks for the info! I'm glad to know it can be done and it's definately going to be my next project.

GaryB, do you have the full schematic scanned for the T1 transport? I would love to receive a copy since it's only a matter of time before I'll find one with my name on it...
 
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VRDS T1

Guido,
The T1 is just a transport, so I suspect the data will be valid. Just in case, the clock frequency is 16.9344Mhz. By the way, the stock VRDS T1 is just an OK transport. I've had it for a number of years (>5) and upgraded it with a low jitter clock and output driver from G+D transforms when they were still in business. The output driver uses some Motoroal ECL drivers and the combination is a big improvement over the stock unit.

Regarding a complete scan of the T1, no I don't have one. Why not just call up TEAC and have them send you a service manual. Thats what I did and it wasn't too expensive. Definitely less than $20.

---Gary
 
Gary,

You are right, if it is only a transport, there is no dig filter.
But it could be that the output is not i2s but some other format!!
Check were the signals are going (spdif transmitter i guess) and if it can handle
i2s and is setup to handle i2s. There are many serial formats..

Did not know it was a transport, don't have one. So i don't need the manual...


What i meant was the I2S clockline frequency, not the xtal freq !!

E.g. in an old philips player with 4 times oversampling:

samplefreq 44.1 kHz = 44100
32 bit data wordlength 44100 * 32 (16 bit unused)
left/right channel in one line 44100 * 32 * 2 = 2.8 MHz clock on I2S clockline

after the dig filter:
samplefreq 44100 * 4 (4 times oversampling)
16 bit data wordlength 44100 * 4 * 16
left/right channel in one line 44100 * 4 * 16 * 2 = 5.6 MHz clock on I2S clockline

So you can see if it is before or after a dig. filter when looking at the I2S clockline freq.
But it depends on the implementation and the wordlenght.

You need to know the freq and wordlenght if you want to connect something. I2S does not spec
wordlength or freq!!

Regards,
Guido
 
The Sony chip outputs EIAJ format, which means the data is right alligned and bck is 48 WCK. The chip has a fout times oversampling filter. Wether or not oversampling is active depends on the pin57. If I remember correct if pin57 grounded then the oversampling is bypassed.
 
Don Juan

Hi DonJuan,
For my experience I prefer pick up the signal netx the resistors these resistor don´t influence in the corren source of 1mA it are in serie configuration and more
and these resistors are for the adapter the line to DAC, my experience is that before en ln digital lines and source clocks I have more overshooting + ringnig
these overshooting have High Frecuency componets and this is no good for me, and netx these high frecuency are muffed
next the resistors.

In the RM20 you can see that resistors are next the NPC digital filter, I think that is an integrate DAC but in the case of Gary, he has a Transpor and he needs an
external DAC, also I suposse that Gary needs before pick up next the resistor he needs a buffer for external output becouse is not recomendable pick up without bufer for external source or he nedds on tratament of these signals before tha external source..

Excusme for my bad english.

Jesús Puerto.
 
I2S Clock line frecuency

Hi Guido,
The clock line in the I2S format SCLK depen of the Clock and Disc Speed Factor
and how the DATA and the LRCK depen of the SCLK in the formats are .
MSB first and Fs is (44.1xn)Khz where n is
the speed.



:drink:
Excuseme tomorrow more, but now beginin my favorite futbol match.

Manchester/ R.Madrid

Jesús
 
Jesus (sorry about the 'u'),

The clockline in I2S does NOT depend on the clock (you mean xtal?) and disk speed.

The xtal of the player does not matter, it is divided internally in the decoder, before it is used to create the I2S signals.

The I2S signal is located behind the decoder, it is not varying on disk speed. You don't have different samplingfrequencies for the audio signal at the start and end of a disk, it is all 44.1 kHz. So when you know how the dig filter and/or dac get their data, you can calculate how many clockpulses are needed to read one sample. See the previous post. Then you know the frequency
of the clockline.

Since the bits on the disk are not stored with the same density, the speed of the disk changes during playing to keep the data, coming out of the decoder, at the same rate (=fixed samplingfreq).

And if i look at fcserei's post it is not I2S format and it is oversampled (pin57 is floating=high=not bypassed) ???

Guido
 
Guido and I2S

Hi Huido,
You are right, I wanted say the Xtal and the speed of the disc in look to disk mode you con see my information in the data sheet of the SAA7372 pages 8 and 16.
And we can see in the page 4 the block diagram that the signal pass next the SRAM at the audio procesor and next the serial data interface that it is the source of I2S signal.
:goodbad:
And also you have reasson about the frecuency source of I2S .
SCL= 2.8224 bits/s a binary flow twice bigger that the standart flow 1.4112

The best regards.

Jesús
 
fcserei said:
The Sony chip outputs EIAJ format, which means the data is right alligned and bck is 48 WCK. The chip has a fout times oversampling filter. Wether or not oversampling is active depends on the pin57. If I remember correct if pin57 grounded then the oversampling is bypassed.

This must be wrong....when looking in the data-sheet the pin57 is marked: 4.2336MHz output. Subject to vari-pitch control.

The data-sheet is to big for posting....:(
 
Here is the first page in datasheet:

What do they mean by: Digital spindle servo system (incorporating an oversampling filter)

Is there a filter present to prevent the servo system to go bananas because of noice, or is it a digital oversampling filter active in the chip's sound-processing ?????
 

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