stereo DAC chip such as ad1853, cs43122 can be wired to mono application to achieve better S/N and interchannel isolation. there are some hifi products apply this technology, mark levinson no390s use two ad1853 and marantz sacd 14 use two cs4397. my question is about how to do it.
question1: about the digital process, in ad1853 datasheet, page 16, they say "right channel digital data must be inverted", does it enough in digital part? can anyone explain it with I2S format detail?
question2: about the analog output, how can i connect voltage output dac's(cs4397, cs43122) output together?
question1: about the digital process, in ad1853 datasheet, page 16, they say "right channel digital data must be inverted", does it enough in digital part? can anyone explain it with I2S format detail?
question2: about the analog output, how can i connect voltage output dac's(cs4397, cs43122) output together?
Reply 1 1/2
AD 1853 etc. are far too complicated for amateurs to use in mono mode. Don't get me wrong, the chips are great but require an insane amount of support circuitry -- my telephone concalls with the specialists at Analog Devices reveal that AD recommend a DSP for the inversion.
I am not intimately familiar with the Crystal units. However, voltage output units can be paralelled directly, usually through a series resistor to a summing point.
Petter
AD 1853 etc. are far too complicated for amateurs to use in mono mode. Don't get me wrong, the chips are great but require an insane amount of support circuitry -- my telephone concalls with the specialists at Analog Devices reveal that AD recommend a DSP for the inversion.
I am not intimately familiar with the Crystal units. However, voltage output units can be paralelled directly, usually through a series resistor to a summing point.
Petter
PETTER, thanks for you reply.
it¡¯s a challenge to us, and the challenge attract me most, with you information, I think the digital process is as follows, (let¡¯s consider left channel )
1\ convert left channel serial data to parallel data and shift it to a register.
2\ use SCLK clock the data out twice, one for chip¡¯s left channel with LRCK high, one for it¡¯s right channel with LRCK low. if we connect analog output like ad1853¡¯s datasheet, with L+ to R-, L- to R+, we need to invert the right channal data. if we connect analog output with L+ to R+, L- to R-, we need not invert the data. I guess the former may has some advantage, it may neutralize some random noise. (I wonder if inverted digital data input= inverted analog output? )
If the process is as described above, the remain question is how to realize it, use DSP may be a easy way when one has develop platform. use EPLD or FPGA may be a good solution, we can also use classic logic parts.
it¡¯s a challenge to us, and the challenge attract me most, with you information, I think the digital process is as follows, (let¡¯s consider left channel )
1\ convert left channel serial data to parallel data and shift it to a register.
2\ use SCLK clock the data out twice, one for chip¡¯s left channel with LRCK high, one for it¡¯s right channel with LRCK low. if we connect analog output like ad1853¡¯s datasheet, with L+ to R-, L- to R+, we need to invert the right channal data. if we connect analog output with L+ to R+, L- to R-, we need not invert the data. I guess the former may has some advantage, it may neutralize some random noise. (I wonder if inverted digital data input= inverted analog output? )
If the process is as described above, the remain question is how to realize it, use DSP may be a easy way when one has develop platform. use EPLD or FPGA may be a good solution, we can also use classic logic parts.
Hey gringo,we dont need no steenking dsp!!
A DSP chip is not necessary. Using one would be akin to raising Tower bridge to let a canoe through. I cite in defence of the above, the outboard dac design in the 4/96 issue of Audio Electronics.
This design, by an AD employee, using the CS8412, AD1893, SM5813 and AD1862(x2) clearly shows phase inversion being accomplished by inverting the seperate left and right datastreams as they exit the SM5813 using a 74HC04 inverter. I have seen this done in a number of commercial and DIY schematics.
Of more interest is a Bitstream design in the september and october 1990 issues of Hifi News. In this design the inverted L/R datastream is created by feeding the normal L/R datastream to both inputs of a two input nand gate ,a 74HC132. The +L/-L and +R/-R datastreams are then created using a dual 64bit shift register (4517) and a dual 2 to 1 multiplexer (74HC157) and fed to a SAA7321 each. A 24 bit design using a CS8420 and a CS4397/43122 would need one more 4517 shift register but it would be better to use a FPGA. All the clock generation could then be done in it and depending on the size one could go off on a tangent and implement a FIFO and/or a PLL or DLL or even a DPLL along the lines of a 74HC297 and those who think paradise is an array of dials like the one in the Krell control room in the film Forbidden Planet could decode the CD subcode and display it along with some kind of level display.
ray.
A DSP chip is not necessary. Using one would be akin to raising Tower bridge to let a canoe through. I cite in defence of the above, the outboard dac design in the 4/96 issue of Audio Electronics.
This design, by an AD employee, using the CS8412, AD1893, SM5813 and AD1862(x2) clearly shows phase inversion being accomplished by inverting the seperate left and right datastreams as they exit the SM5813 using a 74HC04 inverter. I have seen this done in a number of commercial and DIY schematics.
Of more interest is a Bitstream design in the september and october 1990 issues of Hifi News. In this design the inverted L/R datastream is created by feeding the normal L/R datastream to both inputs of a two input nand gate ,a 74HC132. The +L/-L and +R/-R datastreams are then created using a dual 64bit shift register (4517) and a dual 2 to 1 multiplexer (74HC157) and fed to a SAA7321 each. A 24 bit design using a CS8420 and a CS4397/43122 would need one more 4517 shift register but it would be better to use a FPGA. All the clock generation could then be done in it and depending on the size one could go off on a tangent and implement a FIFO and/or a PLL or DLL or even a DPLL along the lines of a 74HC297 and those who think paradise is an array of dials like the one in the Krell control room in the film Forbidden Planet could decode the CD subcode and display it along with some kind of level display.
ray.
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