What's up with SRC's

[jwb]

I don't think your argument is relevant. You can generate the bitclock (1:1) and word clock (1:32) from the master clock, and you can separate the left and right streams from an IIS stream using shift registers. Furthermore, the separation between "the filter" and "the DAC" is not absolute. Most DACs these days have the filter built-in. Some lack a filter, and some can use an external filter to bypass the internal one.

[rfbrw]

Originally posted by jwb
I don't think your argument is relevant. You can generate the bitclock (1:1) and word clock (1:32) from the master clock, and you can separate the left and right streams from an IIS stream using shift registers. Furthermore, the separation between "the filter" and "the DAC" is not absolute. Most DACs these days have the filter built-in. Some lack a filter, and some can use an external filter to bypass the internal one.

Either by accident or design you seem to be missing the point.
Having gone to effort of using the ASRC in the the belief that it will provide a cleaner set of signals you then set about demultiplexing the serial data and passing it through large shift registers undoing all the good work. If you choose to bypass the digital filter or need to use an external one you still cannot clean up the signals just prior to the dac with anything other than flip-flops assuming you choose to forego PLL's. And just before the dac is where the cleaning needs to be done for best effect.

[jwb]

I must be missing the point by accident, because I'm still not with you! I don't use an ASRC to "provide a set of clean signals." I use an ASRC to bridge two clock domains: the S/PDIF embedded clock, and the master clock in the DAC. I know that the signal emerging from the ASRC is clocked on my master oscillator, so I don't need to use PLLs and VCXOs to maintain signal integrity. In the DAC's clock domain, only one thing matters: the quality of the word clock. This is the signal the DAC chip uses to lock a word into its internal registers. The digital filter will have outputs with poor timing, but who cares? Any jitter on the data lines is irrelevant, assuming the setup and hold times are met. The bit clock and word clock produced from the digital filter can be ignored by simply discarding them. The DAC chip can then be operated directly from your own oscillator.

Sorry if I'm ignoring something obvious.

[Guido Tent]

Originally posted by Norman Tracy

I have wittnesed the CS8420 in my XD0 and X-DAC 3.24 designs get into this mode both on my bench and in the listening room. In this "invalid mode" the CS8420 DSP has bad coefficients and generates notches in its output frequency response and spurious tones. On the bench one can see these as bursts of noise.

Hi Norman,

Does MF have supporting firmware to work around this bug ?

best