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Old 4th December 2001, 07:11 AM   #1
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Could anybody please help tell me how can i reduce phase noise when i using a pll circuit? I want to build a pll to suite the ferquency from 11MHz to 25MHz, how can i do this?
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Old 12th December 2001, 01:19 AM   #2
Dave is offline Dave  New Zealand
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PLLs are tricky to design and very expensive.

I considered one for my next project but now I am working on a system using an Analog Devices Direct Digital Synthesis chip combined with a FIFO.

Take a look at my site -

http://www.geocities.com/d_broadhurst/index.html
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Old 14th December 2001, 02:42 AM   #3
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Hill,
I'm not sure what you are want to do. Do you want a Pll circuit that sweeps or steps from 11Mhz to 25Mhz or a circuit that will lock a 25Mhz signal to a 11Mhz reference ? Either way, Philips Semiconductor have a 70page design guide for their 4046,7046 and 9046 HC/HCT series plls available by request at
http://www.philipslogic.com/products/hc/ . The PLL Design Guide request information is at the bottom of the page along with some design software. National Semiconductor www.natsemi.com
also have data on pll phase noise and though most of it refers to the GHz spectrum the general principles should still apply.
HTH ray.
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Old 15th December 2001, 06:35 AM   #4
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ray,

Aha, at facts I want to design a pll circuit which can sweeps from 11Mhz to 25Mhz with low phase jitter.
But i don't know how i can design a boardband vcxo with low jitter. I'd browse any website, i could not found the boardband vcxo yet. But i think the DDS technology is the best chioce.

hill
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Old 15th December 2001, 07:03 AM   #5
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Can you explain why need such a wide range and do you actually need it to sweep from 11Mhz to 25Mhz or do you need a number of spot frequencies between 11Mhz and 25Mhz?

ray.
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Old 15th December 2001, 04:34 PM   #6
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Ray,

Because i want to use the circuit to suite all of the digital audio source. They'er HDTV(32k samping rang), CD(44.1k), MD(48k), DVD(96k)., the system clock of them will start from 8.192MHz to 24.576MHz. So i need the boardband oscillator, my idea is right?

hill
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Old 16th December 2001, 12:01 AM   #7
Dave is offline Dave  New Zealand
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Hill,

You can't build a VCXO based PLL to lock to every frequency in that range.

You use two VCXOs. One is used to lock to frequencies which are a multiple of 44.1 KHz - 44.1, 88.2 etc. the other locks to multiples of 48 KHz - 48, 96, 192.

You need the appropriate dividers (to divide the output of the VCXOs to get to the lower sampling rates) and switching logic to switch between VCXOs and divider outputs.

You will probably want to use the 9046 for the phase comparator. It is a charge pump and is the most advanced one I know of. It does not suffer from something which I think is called backlash.

After that you need to get VCXOs custom cut to the exact frequency you need ($$$$.$$) - they should have a pull range around 400ppm.

Next you'll have to design the loop filter - the most critical part.

I gave up at this stage and started designing my FIFO based solution which is coming along quite nicely.
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Old 16th December 2001, 08:59 AM   #8
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The AD98xx approach will probably prove easier and more accurate given what you want to do. It woud also need fewer chips as the AD98xx chip would output the exact frequency you want under under the control of PIC or AVR micro. The only minus point I can see is if you want to lock to an external signal, for example the Fsync/Wordclock output of a CD player or DAT machine.
I would have to disagree with Dave on PLLs. The dividers are trivial and Vcxos are readily available where I am (UK). As with all analogue design trade-offs are involved but loop filters are not nearly as difficult as Dave seems to suggest.

ray.
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Old 16th December 2001, 09:37 AM   #9
Dave is offline Dave  New Zealand
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rfbrw,

I realise the PLL filter is workable but I found trying to source VCXOs very, very difficult. In the end I decided on the DDS solution which I think will provide better performance. It would also be cheaper than the VCXOs.
I am using an AVR micro to control it.

Dave.
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Old 16th December 2001, 03:25 PM   #10
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Dave,
Dont get me wrong I think the DDS approach is much better than using an analogue PLL. The only is that I could not find a method of locking to an external reference without using a VCXO, which is probably cheaper these days than a K-grade BB PCM63, or somehow digitizing the error signal and controlling the AD98xx
that way.

RAY
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