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#31 |
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diyAudio Member
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thanx.
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#32 |
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diyAudio Member
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this is off topic, but while i've got jocko's and fred's attention...
have you guys heard of this ERS material? i mention it in another thread... carbon fibre fabric impregnated with strands of metal alloys... supposedly derived from military stealth/diplomatic quiet-room applications. have you encountered this in the telecom industry? |
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#33 |
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diyAudio Member
Join Date: Jul 2002
Location: Germany
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Well, as far as i know the SACDs of Sony use a 45MHz clock.
45MHz is a bit much for standard HC logic, isn´t it? I have replaced it in my Sony DAC to a VHC inverter and sound became definately better - no doubt! It is fed with 49.125 MHz
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If time permits - stuff some parsley in your ears and listen how it grows! |
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#34 |
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diyAudio Retiree
Join Date: Oct 2002
Location: Spain or the pueblo of Los Angeles
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"Interesting that after AC logic was introduced, a whole new class of CMOS with faster edge rates than HC CMOS but addressing the shortcomings of AC CMOS"
And VHC is one of those families. I notice you didn't use AC CMOS. |
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#35 |
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diyAudio Member
Join Date: Apr 2003
Location: Sweden
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I think rbroer has a point afterall:
Typical PLL stops working on a quite high freq due to that the receiver chip needs to have a sufficient capture range. Mechanical feedback when playing loud would most certenly come into play. By freeing the osc from the chassis, the frequency which would influence the osc will rise considerally and maybe end up within the PLL (>1 khz?) range and thus filter out the contribution from mechanical feedback. / |
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