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Old 23rd July 2008, 01:25 AM   #1
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Default Reclocking balanced PCM63

I'm attempting to work out a reclocking schema for a Pass D1 derived DAC. The plan is to adapt the schema proposed on the Audio DAC pages for use with the balanced DAC's. http://members.chello.nl/~m.heijlige...tml/dactop.htm

Everything seems relatively straight forward except how to best to handle inverting the L and R data lines. I was initally considering using the q-bar outputs but came across a thread which suggested there is a delay of roughly 150ps between q and q-bar. I'm not sure how significant this timing difference actually is, but it does make me wonder if I would be better off using XOR gates at the input to the reclocking 74HC175's and use only the q outputs to ensure data is clocked out simultaneously?

any thoughts?

cheers
Paul


note: U5 = 4HC02, U3 = 74HC175
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Old 23rd July 2008, 02:02 AM   #2
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150pS skew would not be an issue in this location. What is important is the bit clock arrives sufficiently later (usually half to one master clock cycle later) to clock in the data bits.

The LE signal at the PCM63 is the one to be very nice to. Double buffering (deeper fifo) has sounded better to me. If the DF is an "older" one with a deglitch output, usually one master clock earlier and inverted to the LE signal, re-re-re-reclock it to get a deeper fifo and better jitter rejection. If you have a differential clock, you can ping-pong the d flops to get double the number of stages in at the same time delay.

Good to see interest in the classic PCM63. It can be very enjoyable, involving, musical.

Share and Enjoy,

WMS
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Old 23rd July 2008, 02:28 AM   #3
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WMS,

Thanks for the advice. I wasn't sure if the critical point for timing was loading data into the DAC. Using q-bar should simplify things quite a bit. I'll try getting the modified Tent schema working before delving into re-re-reclocking

I realise I'm going to be better off with picogates, but if I stick with 175's I seem to have two options:
a) run LE thru one '175 and data thru a second.
b) use a '175 located close to each pair of pcm63 and reclock data and LE at this point.

I'm tempted to use option b as this allows '175s to be located very close to the DAC's will allow trace lenghts to be better matched.

DF is SM5842APT, and the clock is a Tent VCXO.

cheers
Paul
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Old 24th July 2008, 10:07 PM   #4
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Attached is an "in progress" schematic. It's based on the Pass D1 front end with the following changes:

a) Jocko Homo's spdif input replacing everything up to the CS8412/4
b) D1 VCXO/PLL modified to work with the Tent Labs VCXO
c) Audio DAC project reclocking schema modified for balanced operation, replacing the XOR gates used in the D1.
d) Provision for WMS loop filter mod

Most component values, power supply and other details are still missing.
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Old 24th July 2008, 10:19 PM   #5
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Hit post a little too quickly...

I'm a bit puzzled about how to best handle the series termination on the lines from the DF to 175's and the LE lines from 175 to dacs. I've read somewhere that it's best to split the lines at the source and add series termination to each of the lines. This is what I've done on the LE outputs. Is this worth doing on the lines from DF -> 175's and should I also use this strategy on the CLK line to the individual dacs?


cheers
Paul
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Old 29th July 2008, 05:31 AM   #6
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Attached is a more complete schematic on the proposed dac front end.

There are still a number of gaps but this is getting much closer to being complete. Hopefully this looks reasonably sane?


cheers
Paul
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Old 29th July 2008, 07:33 PM   #7
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Quote:
Originally posted by spzzzzkt
Attached is an "in progress" schematic. It's based on the Pass D1 front end with the following changes:

a) Jocko Homo's spdif input replacing everything up to the CS8412/4
b) D1 VCXO/PLL modified to work with the Tent Labs VCXO
c) Audio DAC project reclocking schema modified for balanced operation, replacing the XOR gates used in the D1.
d) Provision for WMS loop filter mod

Most component values, power supply and other details are still missing.
please get rid of HC4046 or derivatives, these are horribly noisy.........

then keep up the good work !

best
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Old 29th July 2008, 08:58 PM   #8
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Hi Gudio,

Thanks for the advice - I'll look at some alternatives for the PLL. At this rate I'm in danger of ending up being a direct lift of the Audio DAC front end - not that would be a bad thing given it's pedigree

cheers
Paul
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Old 30th July 2008, 07:37 AM   #9
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Quote:
Originally posted by spzzzzkt
Hi Gudio,

Thanks for the advice - I'll look at some alternatives for the PLL. At this rate I'm in danger of ending up being a direct lift of the Audio DAC front end - not that would be a bad thing given it's pedigree

cheers
Paul

Hi Paul

Get the point, we have saying like " beter goed gestolen dan slecht bedacht ", you are free to use the design for your own purpose

cheers
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Old 30th July 2008, 07:57 AM   #10
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Hi Guido,

Thanks for clarifying the situation on reuse of the circuit. I'm also looking at doing something like Jos Van Eijndhoven's pic based pll. http://www.eijndhoven.net/jos/dac2/index.html

Obviously that is significantly more diy...

cheers
Paul
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