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Old 18th March 2003, 03:23 PM   #1
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Default and this circuit

and this
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Old 19th March 2003, 01:29 PM   #2
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yeah - it could have metastability issues.

Jim.
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Old 19th March 2003, 01:39 PM   #3
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Solution to metastability issues:

Use the other flip-flop(FF) that you have on that IC.
Connect the Q output of the first FF to the D input of the second.
Take the Q output of the second FF and use this as the output.
Connect your clock signal to the clock input on both of the FF's.

This is a standard anti-metastability circuit.


Jim.
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Old 17th June 2003, 12:15 PM   #4
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Default AES out

hi, how to connect this circuit to AES out? thank you
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Old 17th June 2003, 12:54 PM   #5
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It is interesting to see that meta-stability and the standard cure
against it seems to be quite well-known. When I worked with
digital design professionally almost 20 years ago it was a
largely unknown phenomenon. I remeber learning about it
from an AMD TTL databook/app.note/whatever which described
the phenomenon and claimed that AMD flip-flop were less
susceptible to this by having a much narrower time window
during which the input must not change.

Of course, coping with meta-stability is necessary in these
applications.
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