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Old 2nd July 2008, 02:52 AM   #1
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Default Haiku I/V Stage

Greetings,

Today I have successfully tested a new I/V stage I designed to be used with the PCM1794A and the ESS9008 (though it will work with almost any current output DAC).

The design is loosely based on Nelson Pass' D1 MOSFET I/V stage, but my circuit has some unique features.

I chose to use a CCS load for both the casocde and the output emitter follower. I also made use of parallel devices (because the DACs I am using put out a lot of current) and voltage references. Obviously I chose BJTs instead of FETs and I also use +15V and -5V.

I have not measured it yet, but it sounds great. The simulations look very good, but I know they can't really be relied on.

Here is the CCT schematic. I hope some of you find some use for it in your own projects.

The circuit as shown is configured for the Buffalo(ESS9008) DAC with balanced output of 2VRMs at 0db.

VR3/VR4 set the bias current through the common base amplifier. I found the best results so far by adjusting these until the voltage at the bases of Q11/Q12 was about 6V

VR1/VR2 are used to adjust the voltage at the virtual GND input to 0V

As always, any constructive feedback welcome.

Cheers!
Russ
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Old 2nd July 2008, 03:07 AM   #2
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Looks very interesting to me, Russ, as I'm a fan of Nelson Pass' work. I'll be keeping my eye towards this thread and possible IVY vs. Haiku comparisons.
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Old 2nd July 2008, 04:31 AM   #3
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Why BJTs over FETs?
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Old 2nd July 2008, 08:12 AM   #4
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THX Russ, great ! What need to be changed to make it work as well with a 1794 ? Can you give us the correct values for that one, too ? THX a lot !
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Old 2nd July 2008, 09:15 AM   #5
Mazuki is offline Mazuki  United States
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Quote:
THX Russ, great ! What need to be changed to make it work as well with a 1794 ? Can you give us the correct values for that one, too ? THX a lot !
And TDA1541 too
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Old 2nd July 2008, 09:20 AM   #6
t5 is offline t5  Germany
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what's the estimated current draw of one balanced haiku i/v stage?
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Old 2nd July 2008, 09:56 AM   #7
timpert is offline timpert  Netherlands
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Interesting circuit. I have considered a setup like this myself. Although I never came to a physical implementation of my ideas, and your I/V concept looks really mature to me, I would like to share some contemplations I had when drawing mine up.

I wonder (nitpicking alert!), wouldn't your current sources be more stable hen you connect the ref input of the TL431 to the emitter of one of the current source transistors, instead of to its base? See page 6 on the Fairchild datasheet .

Furthermore, I would consider to generate the base voltage for Q5/6 with an identical transistor connected as a diode with the same bias current, to add thermal tracking. If that's not enough still, it might even be an idea to cascode Q5 and Q6 with an additional transistor, biased by another diode connected transistor in series with the base bias transistor, so both Q5/6 and their base bias transistors have identical Vce, identical dissipation and, when mounted in thermal contact, very good thermal tracking. This ensures that your DAC current output stays at 0V over a wide temperature range.

I didn't find an off-zero output voltage tolerance specification in many DAC datasheets (the TDA1541A sheet states 25 mV though as an exception), but many state that the current output should be held to GND as close as possible.

On the workbench, the benefits of these measures might not stand out immediately or even at all. But in an enclosure, with no knowledge where it is going to be used (on a cold floor, close to a warm lamp, or on top of a hot amplifier), thermal tracking might even prevent a situation where, on one occasion, sound is stellar, and on the other it sounds only so-so. The latter usually occurs when friends are around...
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Old 2nd July 2008, 10:23 AM   #8
timpert is offline timpert  Netherlands
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I mean like this. And then thermally couple Q5 to the transistor to the left of it. All four transistors of the same type. And then null the input by adjusting the current through the bias transistors.
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Old 2nd July 2008, 11:35 AM   #9
timpert is offline timpert  Netherlands
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Another thought that popped into my mind during lunch break: isn't it a good idea to use a folded cascode? That way, all signals are referred to ground. In the current situation, the output signal is referred to the positive supply, resulting in practically nonexistent PSRR. The demands on the power supply are quite severe this way.
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Old 2nd July 2008, 12:39 PM   #10
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Wow Timpert, a lot to cover. Thanks for the comments and the input.

I may try changing the VREFs as you suggest, but in practice the way I have them seems to be working great.

The base voltage for Q5/Q6 needs to be adjustable to zero the virtual ground. I am not sure how I would accomplish that using your scheme.

In practice the circuit seems to be thermally stable. I have heated it with a heat gun and the input node only moved about 5mv.

The current through the rest of the circuit is less critical.

I thought about a folded cascode too, and I may try it, but it makes the cct more complex than it really has to be. With a good power supply like the LCBPS things should be just fine. It certianly has no worse PSRR than a D1.

Cheers!
Russ
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