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Old 11th June 2008, 04:16 PM   #1
percy is offline percy  United States
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Default What's wrong with this idea ?

Why do you have to recover the clock from the spdif stream ?
Why can't the sample data bits be extracted from the sub-frame, sent to the dac, followed by a 'latch enable' triggered by the detection of the next sample's preamble ?
Assuming a source/transport that has a pretty good clock to begin with, and a DAC that can work just off LE (latch enable).
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Old 12th June 2008, 03:41 PM   #2
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How would you clock the data into the DAC?
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Old 12th June 2008, 04:45 PM   #3
percy is offline percy  United States
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Do you have to 'clock' the data to the dac ? Depends on the dac you are using. Does a r2r dac need data to be 'clocked' into it ?
You simply put the bits on a register and trigger it.
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Old 13th June 2008, 04:39 AM   #4
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Virtually all DACs use an interface called I2S, which is a serial interface consisting of data, bit clock, and word clock. For more information see here:

http://www.nxp.com/acrobat_download/various/I2SBUS.pdf
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Old 13th June 2008, 12:10 PM   #5
percy is offline percy  United States
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what has happened to this board ??

you need to throw away the books, forget what you have been 'taught', ignore the way things have become ('commercialized') in the world of digital audio and its transmission and start with the very basics, then you might understand what I am trying to say.
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Old 13th June 2008, 12:19 PM   #6
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Hi Percy,

You do have to clock the individial data bits into the DAC.
Typically there is a shift register of some sort acting as a serial to parallel converter inside the DAC.
You need a clock I'm afraid.


Quote:
Depends on the dac you are using. Does a r2r dac need data to be 'clocked' into it ?
You simply put the bits on a register and trigger it.
Because nearly all DACs have a serial data input, most decoders have a serial output (it saves pins on the chip, and thus improves margins), so if you have an R2R DAC that has a parallel input, you'll still need to convert the serial data to parallel, so the shift register moves from inside the DAC to outside.

Quote:
what has happened to this board ??

you need to throw away the books, forget what you have been 'taught', ignore the way things have become ('commercialized') in the world of digital audio and its transmission and start with the very basics, then you might understand what I am trying to say.
?


Cheers,
Phil
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Old 13th June 2008, 12:22 PM   #7
percy is offline percy  United States
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the clock that you are referring to is different from the "data rate" clock and has no relevance to the rate of flow. they both can be independent of each other.
you would need a pic/mcu of sorts to implement this idea and ofcourse the pic will need a clock to operate but that is not the same clock as the audio signal clock.
makes sense ?

for example, if that clock was way faster than the data rate then would it matter ?
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Old 13th June 2008, 01:01 PM   #8
phofman is offline phofman  Czech Republic
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IIRC, some DACs triggered the output sample and hold circuit by the LR clock, some by the bit clock. But I may be wrong...
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Old 13th June 2008, 01:02 PM   #9
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Hi Percy,
I'm thoroughly confused.

The clock I'm referring to IS the clock used to clock in the data.

Typically, the minimum required signals into a DAC are:

*L/R clock, or LE based signal (a sample clock, if you like) running at either 1x or 2x the sample rate (2x if stereo).
So lets assume 88.2kHz.
*serial data input at a rate of word length x sample rate x number of channels (lets assume 2).
So typically, 16x44100x2 = ~1.41MHz
*A data clock at the same frequency as the data.
So, again, ~1.4MHz.
If oversampling, basically the frequency of all these parameters is multiplied by the oversampling rate.

(I know that it is common to have 32bit words for I2S for instance, I'm just simplifying things a bit).


So, the clock is the same rate as the data rate. If it was faster, it wouldn't work (0101 would be clocked in as 0011 0011 if the clock was 2x the data rate).

What clock do you mean?
What do I need a PIC for?

Cheers,
Phil
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Old 13th June 2008, 01:21 PM   #10
oshifis is offline oshifis  Hungary
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Percy, do you mean by "clock" the signal that triggers the conversion? In the R-2R example this would be the signal that switches the registers' output to the ladder network. But where do you get this signal from? Well, you mentined the "peamble" of the next sample. I don't think such thing exists. Let's say all samples are 0s, so that 16 zeroes are clocked in the register (BTW, where is this clock coming from?). Then nothing indicates the beginning of the next sample.
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