Hi there.glad i am a member of this great forum.
I have a question about the above dac.I keep seeing circuits that place an inverter between the one of the two latches and the fsync.This is for separating the left and right stream via the fsync as i do understand.I just can't understand why they place a selector to separate the data to the DR and DL via the fsync.
The dac latches the last 18 bits of data,so i think this is unnessesary?
Or i am missing somthing important??
I would appreciate any help
Thank you
I have a question about the above dac.I keep seeing circuits that place an inverter between the one of the two latches and the fsync.This is for separating the left and right stream via the fsync as i do understand.I just can't understand why they place a selector to separate the data to the DR and DL via the fsync.
The dac latches the last 18 bits of data,so i think this is unnessesary?
Or i am missing somthing important??
I would appreciate any help
Thank you
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