Hi, I'm developing a DSP using the TAS3108 but I'm having issues with understanding how the clocks function.
The parts that I'm including are:
DSP: http://focus.ti.com/lit/ds/symlink/tas3108.pdf
DAC: http://www.datasheetcatalog.org/datasheet/texasinstruments/pcm1730.pdf
ADC: http://focus.ti.com/lit/ds/symlink/pcm1804.pdf
SPDIF Reciver: http://www.cirrus.com/en/pubs/proDatasheet/CS8416_F3.pdf
SPDIF Transmitter: http://www.cirrus.com/en/pubs/proDatasheet/CS8406_F4.pdf
Sampling Rate Convertor: http://www.analog.com/UploadedFiles/Data_Sheets/AD1896.pdf
I wish to run it at 192kHz/24bit.
I have a 12.288MHz clock that will provide the DSP with 2 channel in and out. But will this be able to support the other devices?
Also would I be able to use the SPDIF section like this, I need a way that if there is a (for example) 44.1kHz SPDIF input it uses the AD1896 to give me out 192kHz. However if it is possible to have the entire system switch to 44.1kHz? Would this help jitter problems?
This is my first digital project so correct me if I'm talking garbage, I may have bitten off a bit more than i can chew but I still intend to eat it =].
Thanks.
The parts that I'm including are:
DSP: http://focus.ti.com/lit/ds/symlink/tas3108.pdf
DAC: http://www.datasheetcatalog.org/datasheet/texasinstruments/pcm1730.pdf
ADC: http://focus.ti.com/lit/ds/symlink/pcm1804.pdf
SPDIF Reciver: http://www.cirrus.com/en/pubs/proDatasheet/CS8416_F3.pdf
SPDIF Transmitter: http://www.cirrus.com/en/pubs/proDatasheet/CS8406_F4.pdf
Sampling Rate Convertor: http://www.analog.com/UploadedFiles/Data_Sheets/AD1896.pdf
I wish to run it at 192kHz/24bit.
I have a 12.288MHz clock that will provide the DSP with 2 channel in and out. But will this be able to support the other devices?
Also would I be able to use the SPDIF section like this, I need a way that if there is a (for example) 44.1kHz SPDIF input it uses the AD1896 to give me out 192kHz. However if it is possible to have the entire system switch to 44.1kHz? Would this help jitter problems?
This is my first digital project so correct me if I'm talking garbage, I may have bitten off a bit more than i can chew but I still intend to eat it =].
Thanks.
No this is a complete from scratch system.
Basicly I want to be able to obtain the following:
Analogue in ---> Analogue out
SPDIF in ---> Analogue out
Analogue in ---> SPDIF out
SPDIF in ---> SPDIF out
All with processing in between and at the best possible quality ie: 192kHz/24bit.
I will control the system with a MCU seperately but wat I really want to know is that, a 12.288MHz clock providing the DSP will give me 2 channel I2S but will that clock also support the DAC, ADC, SPDIF to run correctly?
The thing that confuses me is the way system clock frequency is shown in the data sheets.
I understand Fs means sampling frequencey,
I dont understand where system frequency is written like: 64Fs, 128Fs, 256Fs ect and the meaning of dual speed, quad speed and how i can fit this together?
Basicly I want to be able to obtain the following:
Analogue in ---> Analogue out
SPDIF in ---> Analogue out
Analogue in ---> SPDIF out
SPDIF in ---> SPDIF out
All with processing in between and at the best possible quality ie: 192kHz/24bit.
I will control the system with a MCU seperately but wat I really want to know is that, a 12.288MHz clock providing the DSP will give me 2 channel I2S but will that clock also support the DAC, ADC, SPDIF to run correctly?
The thing that confuses me is the way system clock frequency is shown in the data sheets.
I understand Fs means sampling frequencey,
I dont understand where system frequency is written like: 64Fs, 128Fs, 256Fs ect and the meaning of dual speed, quad speed and how i can fit this together?
There will be a few secret handshakes in there for you to decode...
Where are you seeing references to dual or quad speed?
xxx*Fs refers to either: a master clock, ie 256*Fs at 48KHz sample rate (common for studios, DAT, DVD) at 12.288MHz; or a slower bit clock or word clock for clocking in/out data bits of a particular device or subsystem.
I would suggest a modular or expandable approach, and for starters, it may be easier to get things up and running by focusing on the spdif input, adding the A/D later.
It sounds like you are asking if the single 12.288MHz clock could be a system master clock. If the spdif ins and outs will be for 44.1KHz, then the CS8xxx spdif rx/tx chips would not work without (A)SRCs between them and the DSP. Ti 4392 for instance. That would require an additional clock, likely a 256*Fs of 44.1 at 11.2896Mhz for the output ASRC and spdif tx chips.
It has the potential to be a bit messy, but also rewarding. Paying attention to analog and RF layout parameters would be a good thing. More Googling. Low phase noise clocks feeding chips rather than xtals attached to chips will likely sound better.
Ambitious, but why not?
Cheers,
WMS
Where are you seeing references to dual or quad speed?
xxx*Fs refers to either: a master clock, ie 256*Fs at 48KHz sample rate (common for studios, DAT, DVD) at 12.288MHz; or a slower bit clock or word clock for clocking in/out data bits of a particular device or subsystem.
I would suggest a modular or expandable approach, and for starters, it may be easier to get things up and running by focusing on the spdif input, adding the A/D later.
It sounds like you are asking if the single 12.288MHz clock could be a system master clock. If the spdif ins and outs will be for 44.1KHz, then the CS8xxx spdif rx/tx chips would not work without (A)SRCs between them and the DSP. Ti 4392 for instance. That would require an additional clock, likely a 256*Fs of 44.1 at 11.2896Mhz for the output ASRC and spdif tx chips.
It has the potential to be a bit messy, but also rewarding. Paying attention to analog and RF layout parameters would be a good thing. More Googling. Low phase noise clocks feeding chips rather than xtals attached to chips will likely sound better.
Ambitious, but why not?
Cheers,
WMS
Hmm I think I understand a little more now. I see that my ADC and DAC support a 24.576MHz clock for 128fs at 192kHz but my DSP accepts a 12.288MHz clock for 64fs at 192kHz will this ause a problem?
Would I be able to place a 12.288 on the DAC and ADC to obtain 64fs instead of 128fs, or will this not work?
As for the ASRC I plan to use an AD1896 I forgot to mention before, I have no idea what the datasheet is trying to say about setting up the clock :S http://www.analog.com/UploadedFiles/Data_Sheets/AD1896.pdf .
The Low Phase noise clock multiplier you mentioned, would the ICS601 be sufficent?
I'm building bit by bit on seperate boards, I've finished up the analogue section, I shall solder up the second channel later on today, I will hopefully get started with the ADC -> DAC just to play around, and hopefully intigrate the SPDIF in somewhere too.
Would I be able to place a 12.288 on the DAC and ADC to obtain 64fs instead of 128fs, or will this not work?
As for the ASRC I plan to use an AD1896 I forgot to mention before, I have no idea what the datasheet is trying to say about setting up the clock :S http://www.analog.com/UploadedFiles/Data_Sheets/AD1896.pdf .
The Low Phase noise clock multiplier you mentioned, would the ICS601 be sufficent?
I'm building bit by bit on seperate boards, I've finished up the analogue section, I shall solder up the second channel later on today, I will hopefully get started with the ADC -> DAC just to play around, and hopefully intigrate the SPDIF in somewhere too.
Take the 24.576 MHz clock for A/D and D/A, and a simple digital divide by two to get 12.288MHz for the DSP, half of a cmos 74xx74. This way no ASRC or clock multipliers will be needed for A/D >> DSP >> D/A.
In that arrangement, where you will need ASRC is for the spdif in and out, which will presumably be 44.1kHz.
Have a look at the Ti 4192 ASRC. It's datasheet may be somewhat less mysterious. Maybe.
Twisted Pear Audio sells SRC modules with the 4192 quite inexpensively, the "metronome". With the exchange rate, may be cost effective for you.
Cheers,
WMS
In that arrangement, where you will need ASRC is for the spdif in and out, which will presumably be 44.1kHz.
Have a look at the Ti 4192 ASRC. It's datasheet may be somewhat less mysterious. Maybe.
Twisted Pear Audio sells SRC modules with the 4192 quite inexpensively, the "metronome". With the exchange rate, may be cost effective for you.
Cheers,
WMS
I see so if used http://www.foxonline.com/pdfs/FXO_HC73.pdf (24.576MHz HCMOS Oscillator) to provide to the ADC, DAC, ASRC, SPDIF, I would be able to have all that sorted.
How would I use the 7474 to divide the clock, I've never used it before.
Just also want to clear up, the DSP outputs 64fs with a 12.288MHz clock but wont that cause problems feeding the I2S into the other devices? The ADC, DAC, ASRC and SPDIF all happily accept 24.576MHz clock at 128fs.
Thanks.
How would I use the 7474 to divide the clock, I've never used it before.
Just also want to clear up, the DSP outputs 64fs with a 12.288MHz clock but wont that cause problems feeding the I2S into the other devices? The ADC, DAC, ASRC and SPDIF all happily accept 24.576MHz clock at 128fs.
Thanks.
You are a brave soul! Why the **** not?
The art of analog is as important if not more so when doing mixed signal stuff. Keeping grounds and clocks relatively clean, keeping current loops small and local when possible. You will learn a lot doing this. But you knew that...
The digital divide by two is one half of a 74ac74, 74hc74, or 74vhc74 dual d flipflop, which surprisingly is not so obvious with a google seach:
Feed the 24.xx clock into the ck pin, connect the d pin to the qbar output, tie the clrbar and prbar pin hi to vdd/vcc, take 12.xx clock out of q. For the unused half, tie the d and ck pins to ground, tie the clrbar and prbar to vdd/vcc.
There is a classic book, the ttl cookbook which has the basics of old fashioned logic schemes.
The data between the blocks/modules will be 3 wire: data, bitclock, and wordclock. Or some variation of the three.
The spec sheets will give visuals: Standard which is right justified, left justified, and i2s. Make sure that you have each pair of devices out > in speaking and listening for the same format of 3 wire.
Again, likely that spdif will be 44.1kHz. I'm also guessing that you want 24/192 internally for the DSP to get the highest quality possible for analog in and out. Possibly for live DJing or scratching?
The 8416 for spdif in will not need a clock, as it will generate it's own from the spdif, which will *not* be synchronous with the 24.xx and 12.xx. The 8416 will output 3 wire, of which you can set the format to match what the ASRC wants to hear. Next, the ASRC, either an ad1896 or a ti4192 will use the 24.xx clock to set it's output rate, which will be synchronous with the DSP.
The A/D, being fed by the 24.xx clock will also be synchronous, and will also output 3 wire.
A simple mux, like a 74ac/hc/vhc157 can select either A/D or spdif > ASRC 3 wire for the DSP.
The 24.xx clock can feed the ti D/A for straight 24/192 from the DSP 3 wire output.
Alternatively, I would suggest looking at the ESS Sabre D/A chip. Simpler, and from early reports cleaner than the ti ones. Also able to do more than two channels, in case you get carried away with the DSP and want to output multichannel. For the Sabre D/A, you would not need the 24.xx clock. A separate 40 or even 80MHz clock would be needed.
A second ASRC will be needed for the spdif out. Feed it from the same 3 wire out from the DSP that feeds the D/A, and give it a separate 11.2896 MHz clock to set it's output 3 wire for 44.1kHz. Feed the 8406 spdif driver that 11.2896 clock and the 3 wire from the second ASRC to spew spdif at 44.1kHz.
There are subtleties to cleanly drive a coax out, or just use a toslink.
Cheers,
WMS
The art of analog is as important if not more so when doing mixed signal stuff. Keeping grounds and clocks relatively clean, keeping current loops small and local when possible. You will learn a lot doing this. But you knew that...
The digital divide by two is one half of a 74ac74, 74hc74, or 74vhc74 dual d flipflop, which surprisingly is not so obvious with a google seach:
Feed the 24.xx clock into the ck pin, connect the d pin to the qbar output, tie the clrbar and prbar pin hi to vdd/vcc, take 12.xx clock out of q. For the unused half, tie the d and ck pins to ground, tie the clrbar and prbar to vdd/vcc.
There is a classic book, the ttl cookbook which has the basics of old fashioned logic schemes.
The data between the blocks/modules will be 3 wire: data, bitclock, and wordclock. Or some variation of the three.
The spec sheets will give visuals: Standard which is right justified, left justified, and i2s. Make sure that you have each pair of devices out > in speaking and listening for the same format of 3 wire.
Again, likely that spdif will be 44.1kHz. I'm also guessing that you want 24/192 internally for the DSP to get the highest quality possible for analog in and out. Possibly for live DJing or scratching?
The 8416 for spdif in will not need a clock, as it will generate it's own from the spdif, which will *not* be synchronous with the 24.xx and 12.xx. The 8416 will output 3 wire, of which you can set the format to match what the ASRC wants to hear. Next, the ASRC, either an ad1896 or a ti4192 will use the 24.xx clock to set it's output rate, which will be synchronous with the DSP.
The A/D, being fed by the 24.xx clock will also be synchronous, and will also output 3 wire.
A simple mux, like a 74ac/hc/vhc157 can select either A/D or spdif > ASRC 3 wire for the DSP.
The 24.xx clock can feed the ti D/A for straight 24/192 from the DSP 3 wire output.
Alternatively, I would suggest looking at the ESS Sabre D/A chip. Simpler, and from early reports cleaner than the ti ones. Also able to do more than two channels, in case you get carried away with the DSP and want to output multichannel. For the Sabre D/A, you would not need the 24.xx clock. A separate 40 or even 80MHz clock would be needed.
A second ASRC will be needed for the spdif out. Feed it from the same 3 wire out from the DSP that feeds the D/A, and give it a separate 11.2896 MHz clock to set it's output 3 wire for 44.1kHz. Feed the 8406 spdif driver that 11.2896 clock and the 3 wire from the second ASRC to spew spdif at 44.1kHz.
There are subtleties to cleanly drive a coax out, or just use a toslink.
Cheers,
WMS
Whoa, nice seriously helped =].
I've made the analogue section using the OPA4134, I have a clean supply built too, runs well, gonna buy some shielded audio cables today to remove any input noise. I plan to have 8 channels, but this I will sort out later, I'll stick to stereo while I'm designing. Thanks so much, I'll be putting it together as soon as I get the clock, then I'll post how it goes.
I've made the analogue section using the OPA4134, I have a clean supply built too, runs well, gonna buy some shielded audio cables today to remove any input noise. I plan to have 8 channels, but this I will sort out later, I'll stick to stereo while I'm designing. Thanks so much, I'll be putting it together as soon as I get the clock, then I'll post how it goes.
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