Since some of you are talking about 74HC74s and their replacements with 74VHC74s I thought I'd try this question. The reference to halves in the following referes to the fact that there are 2 seperately usable logic gates on each 74HC74.
The DAC board on my Arcam 6 uses three of these chips, two halves per channel as part of an "integrator" circuit (taking the output from an SM5864AP) and another half to cut the clock frequency from 22MHz to 11MHz for the PCF2705 laser controller chip.
I've just bought a Superclock 1.2 which I've fitted to my Arcam 6. The clock frequency I got was 45MHz (the original was a 22MHz) which I fed through a 74HC74 (there was a spare half unused on the board) and then to the the PCF2705.
The unit still works after this mod but on a scope I can see that the output wave from the Superclock deteriorates the second time through the 74HC74 i.e. it enters at 45MHz happily goes to a buffer amp 74HCU04 and returns to the other half of the 74HC74 happily at 22MHz and then when it comes out again its almost a sine wave at 11MHz.
Is this because the two sides of the chip are interfering with each other because of the speed mismatch? Or is the 50MHz rating a sum of the speeds on each half.
Can anyone think of another reason for this? I'm a bit suprised the chip follows the Superclock's wave shape (a steep rise, small dip and then up again and then negative in a clock cycle) anyway as the spec sheet claims the logic voltages are generated internally rather than just tracking the input. i.e. once I'm over the 1 state the chips should stay at 1 until it drops to 0.
Any insights welcomed.
Bill
The DAC board on my Arcam 6 uses three of these chips, two halves per channel as part of an "integrator" circuit (taking the output from an SM5864AP) and another half to cut the clock frequency from 22MHz to 11MHz for the PCF2705 laser controller chip.
I've just bought a Superclock 1.2 which I've fitted to my Arcam 6. The clock frequency I got was 45MHz (the original was a 22MHz) which I fed through a 74HC74 (there was a spare half unused on the board) and then to the the PCF2705.
The unit still works after this mod but on a scope I can see that the output wave from the Superclock deteriorates the second time through the 74HC74 i.e. it enters at 45MHz happily goes to a buffer amp 74HCU04 and returns to the other half of the 74HC74 happily at 22MHz and then when it comes out again its almost a sine wave at 11MHz.
Is this because the two sides of the chip are interfering with each other because of the speed mismatch? Or is the 50MHz rating a sum of the speeds on each half.
Can anyone think of another reason for this? I'm a bit suprised the chip follows the Superclock's wave shape (a steep rise, small dip and then up again and then negative in a clock cycle) anyway as the spec sheet claims the logic voltages are generated internally rather than just tracking the input. i.e. once I'm over the 1 state the chips should stay at 1 until it drops to 0.
Any insights welcomed.
Bill
I can't explain what is going on here, but I do know that HC logic is generally specified for guaranteed Fmax of 30MHz. My Fairchild 74HC74 datasheet says Fmax=30MHz at Vcc=5V and Cl=15pF. At Cl=50pF Fmax=24MHz.
I would say running the chip at 45MHz is a little dicey regardless of anything else that is going on. I switched to a F(AST) counter when I needed 49.152MHz because I was seeing glitching with HC logic.
I would say running the chip at 45MHz is a little dicey regardless of anything else that is going on. I switched to a F(AST) counter when I needed 49.152MHz because I was seeing glitching with HC logic.
Do you have a TI 74HC74? I did note that the Fmax given by TI is "typical" and not guaranteed. I usually try for circuits that work with worst-case analysis...otherwise you need a logic analyzer to determine if things are actually working.
With a simple circuit like a flip-flop you may well be ok, but even if you are under Fmax you still have to satisfy the setup-and-hold times. Just something to consider whenever you get close to design limits.
With a simple circuit like a flip-flop you may well be ok, but even if you are under Fmax you still have to satisfy the setup-and-hold times. Just something to consider whenever you get close to design limits.
billyboy said:
Hi
Never use more than one gate of each chip. Reading above, the superclock is fed through a divider and a buffer, which deteroriates the performance anyhow. Best you can do is find a clock at the right frequency.
By the way, the PCF2705 is not a laser controller, it is an I2S to SPDIF converter
succes
What is this signal driving ? The load is usually responsible for waveform degradation (too much capacitance?). Chips also burn out - CMOS chips can be damaged by static and proper handling precautions should be followed as partial damage can be insidious.