Finally, an affordable CD Transport: the Shigaclone story

I'm puzzled. I have built 4 of these JohnW regs and have not seen this. Please measure the dc voltage at every pin of 5534. Report here. I'll do the same.


Disconnect opamp output from C906, place some 1k and up from opamp output to ground, measure voltage at all opamp inputs and output (all should be at the same DC voltage 2V5).


I hooked the output to a 1k resistor and ground and the output voltage is 4.1v
Right now I am using a 7805 for pre-reg, is this correct? or do I need to supply the NE5534 with a bi-polar power supply?
 
I hooked the output to a 1k resistor and ground and the output voltage is 4.1v

Assuming your wiring IS correct, I think you have a bad NE5534...it should work (as datasheet says) as buffer (unity gain stable) at 5VDC supply min.
You should try another opamp specified for 5V supply, unity gain stable, high speed, low noise.
Right now I am using a 7805 for pre-reg, is this correct?

It's ok.

do I need to supply the NE5534 with a bi-polar power supply?

Just find the right opamp for application
 
Are all 3 pins (VDD,VVDD and XVDD) using the same voltage ? I saw that VDD is marked as 3.3V but nothing on VVDD and XVDD.

Yes thay are, but there is very good reason (jitter) why you need very, very low noise, high BW, reasonable low impedance voltage regulator for 1) XVDD (x-tal oscillator supply), 2) VVDD (PLL power supply), and 3) VDD (the rest of the digital system supply).

Think simple...like super shunt voltage regulator based on J-fet current source, 3 LED diodes stack in series for 3 x 1V7 = 5V1 bypass with Os-Con cap. You are done, enjoy :)
 
Yes thay are, but there is very good reason (jitter) why you need very, very low noise, high BW, reasonable low impedance voltage regulator for 1) XVDD (x-tal oscillator supply), 2) VVDD (PLL power supply), and 3) VDD (the rest of the digital system supply).

Think simple...like super shunt voltage regulator based on J-fet current source, 3 LED diodes stack in series for 3 x 1V7 = 5V1 bypass with Os-Con cap. You are done, enjoy :)

By looking at the schematic, pin 6,22 and 62 are feeding from L901 via the +8V input from CN902, how des the 8V drop to 3.3V for feeding these 3 pins? If those pin require 3.3V then can I cut the trace and feed a 3.3V directly from a SuperReg?

Thanks
 
Look better, pins 6/22/62 are feed from pin 11/IC903 (regulator +5VDC output), so all supply for IC902 is +5VDC. So for start you can carefully lift pins 6/22/62 from pcb, connect them together in one single point, and inject +5VDC from regulator of your choice. But, remember two things:

1) you should prevent IC902 from latch-up, meaning IC902 should not be powered up before IC901 wich send digital signals to IC902...you see, first supply signal then power up, that's how you prevent from latch-up. Find post from ilimzn at digital section about latch-up, and all will become clear how to deal with it.

2) at a freq. of 16.9344MHz you will gain wery little from Walt Jung SupeRegulator or similar series regs. You need a super-shunt (also called parallel) voltage regulator (super in front off shunt means shunt regulator is feed from active CCS (constant current source) instead of plane (preferable high value) resistor. High impedance of CCS in front of shunt offers high isolation from the rest of system...IC902 will live/work in it's own space, far away from disturbance from say, servo system, motor, LCD display etc.

3) You may try hybride super-shunt regulator, but at a system clock of 16.9344MHz you will need to use high speed current feedback opamp, capable to work on +5VDC supply, low noise, etc...You see, at that freq. low output impedance does not comes from opamp, it's the regulator output capacitor that provides low output impedance at tens of MHz and more. Therefore, use simple, low noise super-shunt with HQ output capacitor.
 
Look better, pins 6/22/62 are feed from pin 11/IC903 (regulator +5VDC output), so all supply for IC902 is +5VDC. So for start you can carefully lift pins 6/22/62 from pcb, connect them together in one single point, and inject +5VDC from regulator of your choice. But, remember two things:

1) you should prevent IC902 from latch-up, meaning IC902 should not be powered up before IC901 wich send digital signals to IC902...you see, first supply signal then power up, that's how you prevent from latch-up. Find post from ilimzn at digital section about latch-up, and all will become clear how to deal with it.

2) at a freq. of 16.9344MHz you will gain wery little from Walt Jung SupeRegulator or similar series regs. You need a super-shunt (also called parallel) voltage regulator (super in front off shunt means shunt regulator is feed from active CCS (constant current source) instead of plane (preferable high value) resistor. High impedance of CCS in front of shunt offers high isolation from the rest of system...IC902 will live/work in it's own space, far away from disturbance from say, servo system, motor, LCD display etc.

3) You may try hybride super-shunt regulator, but at a system clock of 16.9344MHz you will need to use high speed current feedback opamp, capable to work on +5VDC supply, low noise, etc...You see, at that freq. low output impedance does not comes from opamp, it's the regulator output capacitor that provides low output impedance at tens of MHz and more. Therefore, use simple, low noise super-shunt with HQ output capacitor.

You are right on for the 5V, Thanks! I have the Salas SSR1.1 reg and a super reg Positive half (see attachment below), which one you think will be more suitable to supply the IC902?

Thanks

An externally hosted image should be here but it was not working when we last tested it.

U1 is LME49710NA
IC1 is LM336
 
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