Ones and zeros recorded on CDs

[Pjotr]

Hi,

We must not confuse the various kinds of jitter. There is pit jitter at the readout/writing mechanism of the CD reader/writer and there is jitter of the conversion clock at the DA converter. If pit jitter becomes severe this leads unavoidable to readout errors in the digital domain. You get simply wrong data samples. The error correction mechanism handles this and it depends on many factors how well these errors will be corrected and/or concealed.

The other mechanism is jitter of the conversion clock at the DA converter. You can have a complete error free data stream red from the CD, the DA conversion clock jitter still has its audible impact.

Pit jitter does not necessarily degrade DA conversion clock jitter in a well-designed CD/DVD player.

Both jitter mechanisms are completely different but both have their own impact on the final audio quality.

[Guido Tent]

Originally posted by Pjotr
Hi,

We must not confuse the various kinds of jitter. There is pit jitter at the readout/writing mechanism of the CD reader/writer and there is jitter of the conversion clock at the DA converter. If pit jitter becomes severe this leads unavoidable to readout errors in the digital domain. You get simply wrong data samples. The error correction mechanism handles this and it depends on many factors how well these errors will be corrected and/or concealed.

The other mechanism is jitter of the conversion clock at the DA converter. You can have a complete error free data stream red from the CD, the DA conversion clock jitter still has its audible impact.

Pit jitter does not necessarily degrade DA conversion clock jitter in a well-designed CD/DVD player.

Both jitter mechanisms are completely different but both have their own impact on the final audio quality.

Hi Pjotr

Thanks for your reply. Yes you are rigth, too high jitter leads to real errors.

I am very aware of clcok jitter and its' impact (I have my own clocks made on specification) and we desigend a DAC:

http://members.chello.nl/~m.heijlige...tml/dactop.htm

which takes care of jitter to a great extent

Your statement is right, a wel designed player is insensible to incomming jitter. I have yet to see this player.....

In many players the servos affect the playback quality as they induce jitter, regardless of the clock quality.......

best regards

[SY]

Originally posted by Guido Tent


Your statement is right, a wel designed player is insensible to incomming jitter. I have yet to see this player.....

In many players the servos affect the playback quality as they induce jitter, regardless of the clock quality.......

Very interesting. So, if that's the case, there should be data showing effects on the measured output signal of the player. What does that data show?

[Guido Tent]

Originally posted by SY


Very interesting. So, if that's the case, there should be data showing effects on the measured output signal of the player. What does that data show?

Hi

The DAC design in my previous link has a diagnostic output, described in the schematics

http://members.chello.nl/~m.heijlige...ml/dig_r2c.pdf

and here:

http://members.chello.nl/~m.heijlige...LL%20sound.htm

It is a demodulated output which makes it possible to hear the jitter. One of the things you can hear in a badly designed CD player is the spindle motor.......

enjoy

Guido

[SY]

I guess my question wasn't clear. Think of the CD system as a black box. In one end, I put in some data. At the other end I recover an analog signal which goes off to the rest of my stereo system. That's the output I'm talking about.

I'm very curious as to how much, with real world systems, do we see actual measurable differences in the recovered analog signal with things like various bit-for-bit copying schemes and normal variations in CDs and CD playback.

[Pjotr]

Hi Guido,

You are right when it comes to a separate DAC where the DA clock must be recovered. ( No I don’t want to go into a discussion about asynchronous clocking, that belongs to another thread IMHO.)

What I mean by “Pit jitter does not necessarily degrade DA conversion clock jitter in a well-designed CD/DVD player.” is the following: In a “one in all CD player” there is one master clock. That clock goes two ways, it goes a way to the DA converter to clock de DA conversion and it goes away to control the readout mechanism of the CD. It makes sense to put in an “low jitter clock” regarding the DA conversion. I don’t see that in this case the pit jitter degrades the DA converter clock. OK a badly designed CD player … but then there are many complex interactions like feedthrough by PSU lines, gnd loop problems etc.

BTW My compliments for your well documented links

[Guido Tent]

Originally posted by Pjotr
Hi Guido,

You are right when it comes to a separate DAC where the DA clock must be recovered. ( No I don’t want to go into a discussion about asynchronous clocking, that belongs to another thread IMHO.)

What I mean by “Pit jitter does not necessarily degrade DA conversion clock jitter in a well-designed CD/DVD player.” is the following: In a “one in all CD player” there is one master clock. That clock goes two ways, it goes a way to the DA converter to clock de DA conversion and it goes away to control the readout mechanism of the CD. It makes sense to put in an “low jitter clock” regarding the DA conversion. I don’t see that in this case the pit jitter degrades the DA converter clock. OK a badly designed CD player … but then there are many complex interactions like feedthrough by PSU lines, gnd loop problems etc.

BTW My compliments for your well documented links

Hello Pjotr, others,

Pit jitter indeed may ripple through the DACs due to many possible kinds of crosstalk, therefor again, lower jitter means lower reidual artefacts.

Ofcours one may argue where to improve the whole chain, the answer being driven by cost and technical feasibility.

I do not understand asynchronuous clocking sufficiently, in our DAC we designed a cascaded PLL which works very well: Its' immunity for jitter on the SPDIF signal is the highest I have seen among commercial DACs I measured on. Still I can hear differences in transports, therefor the least one can do is reclock the SPDIF signal, using the same low jitter clock.

Thanks for your kind words about our DAC web page and the links.

all the best

[OliverD]

Originally posted by Guido Tent
...in our DAC we designed a cascaded PLL which works very well: Its' immunity for jitter on the SPDIF signal is the highest I have seen among commercial DACs I measured on...

Hi Guido, have you tried ASRC's in comparison? For my understanding, well implemented and fed by a local low-jitter clock source, they should (theoretically) show a much better jitter attenuation than a PLL - however good designed...

What do you think?

[Guido Tent]

Originally posted by AMT-freak


Hi Guido, have you tried ASRC's in comparison? For my understanding, well implemented and fed by a local low-jitter clock source, they should (theoretically) show a much better jitter attenuation than a PLL - however good designed...

What do you think?

Hi AMT freak, others,

I have not used ASRC's (yet)

Can someone explain how and at what cost, a difference in the time domain is being dealt with by ASCR's ?

Be suspicious with respect to the outgoing data of these chips: Their jitter is too high, reclocking is advised !

all the best

[OliverD]

I'm not an expert in DSP, but as far as I understood it, an ASRC is basically a standard oversampling circuit (including a digital filter) that outputs the signal at a very very high fs. In the output section of the ASRC, the very very high fs signal is digitally re-sampled with a much lower, locally generated master clock. Theoretically, the output timing is completely independent (as the "A" in ASRC implies) from any clock signals (and hopefully their associated jitter) before the ASRC.

Doesn't this sound great?

Actually, it's totally different and the "very very high fs" thing is only a model to easier understand the complicated DSP algorithms that are applied to the signal in an ASRC. I still have to look into this.

The CS8420 datasheet has some more info on the subject:

http://www.cirrus.com/en/pubs/proDatasheet/8420.pdf

Of course I understand that the complicated ASRC circuit might introduce even more jitter which could render its benefits totally useless. I'll know more when I have finished my digital pre project.