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Old 27th April 2010, 02:25 PM   #171
adamus is offline adamus  United Kingdom
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that is going to be an expensive build, with a lot of tranformers! I like the idea though.
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Old 27th April 2010, 02:39 PM   #172
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Originally Posted by adamus View Post
that is going to be an expensive build, with a lot of tranformers! I like the idea though.
yes i se. but that is very good for this DAC
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Old 27th April 2010, 04:21 PM   #173
phrarod is offline phrarod  United States
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I've been working with this AN dig board for many years and just built one without half the junk AN put in. You have to be aware that it was not AN UK that designed it but their kit guy back then.

Glad to see you removed the digital filters in later versions of your board. I found the best sound was to come right off the 1865 using a good I/V transformer to a tube buffer out as shown in later examples. I agree SRPP sucks in this case.

I would be very interested in getting one of the dac board and shunt power supply.

BUT what I would be most interested in is developing a battery supply using A123 batteries for the board.

At one incarnation of the FrankenDAC (my name for my two box monstrosity) I could switch battery or AC power. On battery it was STUNNING. However using 3 SLA batteries had its problems which was no dynamics to speak of but wow how quiet and delicate!

The problem for years is SLA batteries are a bad choice just as car batteries are for filament supply. Now with these new A123 batteries they have a impedance of .008 Ohms..

Next if someone could really show a proper schematic to implement I2S into the 1865 that would be a huge leap and allow removal of the receiver chip.

Finally feeding with the M2Tech from computer audio modded to use battery 3.3V for their clocks and I2S output.

NOW you geniuses if you can come up with that it will destroy most dacs you've ever heard for a fraction of the price.

I've built many dacs over the years and keep coming back to the 1865 chip as the most musical and natural. The idea is to refine the circuit to make its as simple and efficient as possible.
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Old 27th April 2010, 11:52 PM   #174
Salas is offline Salas  Greece
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Quote:
Originally Posted by quanghao View Post
I have up dat for DAC-ENd2.
i change all Tl 431 by Salas low shunt. you can se the circuit
Where are the output electrolytics? Will oscillate without.
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Old 28th April 2010, 08:51 AM   #175
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Quote:
Originally Posted by phrarod View Post
I've been working with this AN dig board for many years and just built one without half the junk AN put in.
Hello phrarod

Maybe you know:
1. Why this DAC relay on clock from SPDIF and not using reclocking? How difficult is to add reclocking? Will reclocking improve jitter of this DAC?
2. What changes must done in schematic of digital side to use dual AD1865: L and R channels of one chip in parallel?
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Old 28th April 2010, 02:05 PM   #176
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Quanchao, why did you decided to remove the tl431 ? What is the advantage ?

Thanks,

Davide
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Old 28th April 2010, 07:32 PM   #177
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Originally Posted by Zoran View Post
dac going to conversion just after accepting two words L and R...
not left after received left data word and so...
I think that is not true...
Not exactly this way. After reading CS8414 and AD1865 data sheets carefully I find out that there is delay between channels. On AD1865 "The falling edge of LL and LR cause the last 18 bits which were clocked into the Serial Registers to be shifted into the DACs, thereby updating the DAC outputs." The LL and LR are taken from CS8414 FSYNC output. To get falling edge on LR, when on DL (also DR, serial data inputs from SDATA on CS8414) right channel data data is clocked into the input registers, FSYNC is inverted. Result is 32 clock-beatings delay for right channel what causes 4.08 degrees @ 1 kHz and 81.7 degrees @ 20kHz phase shift.
This happens also on the DCA End 2.
I had not yet analyzed AudioNote schematic between 8414 and 1865 but I think it is better.
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Old 1st May 2010, 11:18 PM   #178
sampler is offline sampler  Lithuania
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Originally Posted by kaameelis View Post
Not exactly this way. After reading CS8414 and AD1865 data sheets carefully I find out that there is delay between channels. On AD1865 "The falling edge of LL and LR cause the last 18 bits which were clocked into the Serial Registers to be shifted into the DACs, thereby updating the DAC outputs." The LL and LR are taken from CS8414 FSYNC output. To get falling edge on LR, when on DL (also DR, serial data inputs from SDATA on CS8414) right channel data data is clocked into the input registers, FSYNC is inverted. Result is 32 clock-beatings delay for right channel what causes 4.08 degrees @ 1 kHz and 81.7 degrees @ 20kHz phase shift.
This happens also on the DCA End 2.
I had not yet analyzed AudioNote schematic between 8414 and 1865 but I think it is better.
Sorry, can't catch your thoughts.... what phase shift and 32 sck delays ?
CS8414 serial out works in mode 6 (L/R, 18Bits LSBJ). Because data is LSB left justified, we have 14 sck cycles before MSB shows up (32 sck in whole audio sample). FSYNC goes directly to left channel latch. So no problems there whatsoever (timing between LSB ant FSYNC falling edge is in accordance with datasheet) . Now right channel latch gets inverted FSYNC with cmos propagation delay (in my case using ST HC04, ~16ns). This has no impact to transition beginning, because of 14 sck cycles before MSB. Now whole sample is fed to DAC, FSYNC goes up, inverts, gets delay from inverter, latches the Right channel DAC with normal delay of "LSB to FSYNC" + 16ns, end of story.

Am I missing something ?
Dunno about Audionote, but there were HC04 in between 8414 and 1685 in some version fur sure. Post a link to some reliable schematics if you know one.
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Old 2nd May 2010, 12:35 AM   #179
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I went through the documentation of the chips, very informative !

Why the CS8414 shown bi-phase coding error in my DAC_END ? Is it supposed to be like this ?

I am very tempted in doing a cute front panel showing the status leds, but I understand I would need a reference frequency to have info in the signal frequency.

D.
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Old 2nd May 2010, 01:09 AM   #180
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Originally Posted by Nikon1975 View Post
I went through the documentation of the chips, very informative !

Why the CS8414 shown bi-phase coding error in my DAC_END ? Is it supposed to be like this ?

I am very tempted in doing a cute front panel showing the status leds, but I understand I would need a reference frequency to have info in the signal frequency.

D.
My be some CS8414 have wrong,
You can conect Jump pin 1 to 2 . Note : led turn on and turn off!
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