Need FPGA experts to review design of Ethernet DAC v2
I have a working ethernet DAC ; the PC sends music using a packetized UDP protocol over Ethernet and a off the shelf FPGA module performs the receiving and outputs I2S. Obviously everything is slaved to the master clock which is 1 cm away from the DAC chip. (http://audio.peufeu.com)
It uses any Linux player. A JACK driver is in the works so it will in the end look just like a regular soundcard (but with 8x 24-192 for digital crossover).
However due to design idiocies in this FPGA module I have been searching for a replacement. I found none, so I started to design a FPGA module with a fast and robust 100 Mbps ethernet connection and fast memory.
Here is the result :
Fully routed, the board uses about 50 cm², or about 7x7 cm. Here is an older version of the layout : http://home.peufeu.com/nik/fpga/board_v02/Layout1.png
Before I go into production, I would be very grateful to get a design review from any FPGA expert here ? Anyone ? I'll build you a shrine ;)
The purpose of this module is very simple : ethernet at one end, 100-pin Hirose connector at the other end, complete microcomputer with Microblaze on the FPGA and memory in between. It will handle the full ethernet bandwidth full duplex, translating this into whatever suitable IO format (including I2S).
Sorry I am not the expert you are looking for. Just to tell you I am very interested in your project (ethernet DAC) for my active 4 to 5 way system with bruteFIR as active filter with linux pc.
I would need 8 to 10 44100hz 24 bit channels.
Would your ethernet project support that much channels ?
In fact it is to replace a maudio delta 1010 soundcard by a device doing the same task but :
with much better sound quality (better dac and dac output circuit)
with all my amplifiers perfectly isolated from PC ground and RFI
thank you very much, Eric, France
If everything goes as planned (:D) it will support 100 Mbps full duplex. Counting protocol overhead etc, count 80 Mbps of audio. That's more than 100 channels of 16/44 (a stupid thing to say, since noone would use that much). I want it to support 8x 24-192 and do active XO using BruteFIR, so our needs are similar.
The current version (Suzaku) nearly does, but has many problems, and the MAC chip on it sucks.
Currently prototype is stalled waiting for the FPGA chips (out of stock at DigiKey, est. lead time end of august). This plus holiday schedules should mean a working prototype by 1-10 of october.
There is no DAC on this module. The DAC is not designed yet ; I will do this in modules. This FPGA thing will output I2S. (and also accept I2S from ADCs for vinyl)
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