Confusion over I2S buffering

[philpoole]

Hi,

I've been studying this I2S buffering circuit from a Philips CD930/940, and I'm a bit confused.
Basically, it is taking the I2S from the decoder output, and prior to sending it to the digital filter, it is inverting the bclk and ws, and delaying the data through a 16 bit shift register.

Now, I can understand what the idea is, delay the DATA by a word, and invert WS accordingly, and invert BCLK so the data is clocked into the shift register when the data is more likely to have settled. And it obviously works.
However, I was of the understanding that the output of the decoder had each sample in the space of 32 clock cycles, not 16 (i.e. 16 bits of data, followed by 16 zeroes for padding) - and I'm pretty sure I've seen that with my oscilloscope, and read it in the datasheet (besides BCLK is 2.8224 MHz, and WS is 44.1kHz).

So, if my assumptions(?) are correct, how can this work? Because WS will not be correctly in sync with the data (I am assuming WS changes on the first bit of a new sample, or some other precise point in the sample - or you won't know where the MSB/LSB is in relation to the rest of the data?

I'm sure I'm just being really dumb here, but how does this work?

[rfbrw]

It is a format converter.

[philpoole]

Ah, as I had suspected, I was indeed being dumb.
Of course. Thanks.

In my defence, I haven't been able to find the datasheet for the SM5840A for love nor money (well maybe not money ).

Cheers,
Phil

[aparatusonitus]

http://www.datasheetarchive.com/sear...840&sType=part

[philpoole]

Nice one.
Thankyou.

This is all starting to make sense now.

[PA0SU]

Looking at my 10 MHz-oscilloscope I found as output from the SAA7310 the I2S as: 'justified left with one bit delay' (MSB left).
The SM5847AF wants: 'justified right'.
Counting well, the data should be shift to the right 15 bits. It looks wonderfull on the scope BUT IT DOES PRODUCE strongly destorted audio after the PCM63's with IV-convertor etc.

The schematic at your question is not to sharp so that I can't read it well. Can you explain me the way the 'format convertor' works?
Thanks in advance.....

[philpoole]

Are you also inverting the clock? As per schematic?
It sounds like your data is either misaligned, or plain wrong.
From briefly looking at datasheets previously, I gather only the SM5480 can output 16 bit data - the later ones start at 18-bit. Is your DAC chip capable of handling 18-bits or more?

[rfbrw]

Originally posted by PA0SU

.......It looks wonderfull on the scope BUT IT DOES PRODUCE strongly destorted audio after the PCM63's with IV-convertor etc.

Are you perchance connecting the SAA7310 directly to the PCM63 ?

[philpoole]

Briefly looking at the datasheets, I think the word length is probably okay, but the bit ordering is reversed.
If that is the case, that will be labourious to sort out.
If it were me, I'd do it with a micro, but it wouldn't be fun (I did it for too long for a day job to enjoy stuff like that any more).

[PA0SU]

I wil explain more:
I DO HAVE a DAC (pre-TentLab product) : receiver: CS8412, digifi: SM4842AP, dac: PCM63, Ten Pierick I/V-convertor.
I'm playing with a CD624-with-rutgerS'Clock & TentLabs SPDIF-refreshing print.
This combination is playing very good.
Next step was: avoid the VCXO in the DAC by transporting the 256.fs Xtal-oscillator signal from the 624 to the DAC. The difference is that large that I formulated the next project: skip the SPDIF, so I started to update another C624.
I tell this because I can compare all signals in my new project with the signals in the TentLabs DAC. This is one of the reasons I use the same (old) chip set.
My question now is:
Why does 'my shift right 15 of DATA' not work (it looks exactly the same as the output of the CS8412 in the DAC) and should the inversion of the CLAB and the WSEL and the shift right 16 of the DATA [if this is the case in the CD930] give good results?