Hi,
I've been studying this I2S buffering circuit from a Philips CD930/940, and I'm a bit confused.
Basically, it is taking the I2S from the decoder output, and prior to sending it to the digital filter, it is inverting the bclk and ws, and delaying the data through a 16 bit shift register.
Now, I can understand what the idea is, delay the DATA by a word, and invert WS accordingly, and invert BCLK so the data is clocked into the shift register when the data is more likely to have settled. And it obviously works.
However, I was of the understanding that the output of the decoder had each sample in the space of 32 clock cycles, not 16 (i.e. 16 bits of data, followed by 16 zeroes for padding) - and I'm pretty sure I've seen that with my oscilloscope, and read it in the datasheet (besides BCLK is 2.8224 MHz, and WS is 44.1kHz).
So, if my assumptions(?) are correct, how can this work? Because WS will not be correctly in sync with the data (I am assuming WS changes on the first bit of a new sample, or some other precise point in the sample - or you won't know where the MSB/LSB is in relation to the rest of the data?
I'm sure I'm just being really dumb here, but how does this work?
I've been studying this I2S buffering circuit from a Philips CD930/940, and I'm a bit confused.
Basically, it is taking the I2S from the decoder output, and prior to sending it to the digital filter, it is inverting the bclk and ws, and delaying the data through a 16 bit shift register.
Now, I can understand what the idea is, delay the DATA by a word, and invert WS accordingly, and invert BCLK so the data is clocked into the shift register when the data is more likely to have settled. And it obviously works.
However, I was of the understanding that the output of the decoder had each sample in the space of 32 clock cycles, not 16 (i.e. 16 bits of data, followed by 16 zeroes for padding) - and I'm pretty sure I've seen that with my oscilloscope, and read it in the datasheet (besides BCLK is 2.8224 MHz, and WS is 44.1kHz).
So, if my assumptions(?) are correct, how can this work? Because WS will not be correctly in sync with the data (I am assuming WS changes on the first bit of a new sample, or some other precise point in the sample - or you won't know where the MSB/LSB is in relation to the rest of the data?
I'm sure I'm just being really dumb here, but how does this work?
Attachments
Looking at my 10 MHz-oscilloscope I found as output from the SAA7310 the I2S as: 'justified left with one bit delay' (MSB left).
The SM5847AF wants: 'justified right'.
Counting well, the data should be shift to the right 15 bits. It looks wonderfull on the scope BUT IT DOES PRODUCE strongly destorted audio after the PCM63's with IV-convertor etc.
The schematic at your question is not to sharp so that I can't read it well. Can you explain me the way the 'format convertor' works?
Thanks in advance.....
Are you also inverting the clock? As per schematic?
It sounds like your data is either misaligned, or plain wrong.
From briefly looking at datasheets previously, I gather only the SM5480 can output 16 bit data - the later ones start at 18-bit. Is your DAC chip capable of handling 18-bits or more?
It sounds like your data is either misaligned, or plain wrong.
From briefly looking at datasheets previously, I gather only the SM5480 can output 16 bit data - the later ones start at 18-bit. Is your DAC chip capable of handling 18-bits or more?
Briefly looking at the datasheets, I think the word length is probably okay, but the bit ordering is reversed.
If that is the case, that will be labourious to sort out.
If it were me, I'd do it with a micro, but it wouldn't be fun (I did it for too long for a day job to enjoy stuff like that any more).
If that is the case, that will be labourious to sort out.
If it were me, I'd do it with a micro, but it wouldn't be fun (I did it for too long for a day job to enjoy stuff like that any more).
I wil explain more:
I DO HAVE a DAC (pre-TentLab product) : receiver: CS8412, digifi: SM4842AP, dac: PCM63, Ten Pierick I/V-convertor.
I'm playing with a CD624-with-rutgerS'Clock & TentLabs SPDIF-refreshing print.
This combination is playing very good.
Next step was: avoid the VCXO in the DAC by transporting the 256.fs Xtal-oscillator signal from the 624 to the DAC. The difference is that large that I formulated the next project: skip the SPDIF, so I started to update another C624.
I tell this because I can compare all signals in my new project with the signals in the TentLabs DAC. This is one of the reasons I use the same (old) chip set.
My question now is:
Why does 'my shift right 15 of DATA' not work (it looks exactly the same as the output of the CS8412 in the DAC) and should the inversion of the CLAB and the WSEL and the shift right 16 of the DATA [if this is the case in the CD930] give good results?
I DO HAVE a DAC (pre-TentLab product) : receiver: CS8412, digifi: SM4842AP, dac: PCM63, Ten Pierick I/V-convertor.
I'm playing with a CD624-with-rutgerS'Clock & TentLabs SPDIF-refreshing print.
This combination is playing very good.
Next step was: avoid the VCXO in the DAC by transporting the 256.fs Xtal-oscillator signal from the 624 to the DAC. The difference is that large that I formulated the next project: skip the SPDIF, so I started to update another C624.
I tell this because I can compare all signals in my new project with the signals in the TentLabs DAC. This is one of the reasons I use the same (old) chip set.
My question now is:
Why does 'my shift right 15 of DATA' not work (it looks exactly the same as the output of the CS8412 in the DAC) and should the inversion of the CLAB and the WSEL and the shift right 16 of the DATA [if this is the case in the CD930] give good results?
I was pointing out, that on the CD930, the output of the 7310 is converted prior to input to the sm5840. I know the 7310 has an I2S output. So it might be that, if the sm5840 outputs the same as it has input, you could perhaps perform the inverse operation to get you back to an I2S signal.
I've no idea if the PCM63 can take an I2S input.
I've no idea if the PCM63 can take an I2S input.
I2S here and there....
First of all: I made a mistake. The digifilter is of course a SM5847 not a 4847.....
The question is that there are at least 6 formats in the I2S! From the SAA7310 the I2S is:'left justified with one bit delay' and the SM5847 needs:'right justified' (both with MSB left).
How to transform from the firts to the second format?
I thought: shift DATA 15 bits to the right, but this does not work!
You gave the suggestion: in the CD930 the WSEL and the BCLOCK are inverted and DATA is shifted 16 bits to the right.
When this should work I begin to become an old man!
I do not understand that at all.
Inverting the WSEL only exchanges left and right and what should happen with the inversion of the bit clock ???? Could be that the timing of the logic is better in this case, but in combination with shift right SIXTEEN of DATA....... ????
I like to understand what I'm doing before doing a lot of labor....
First of all: I made a mistake. The digifilter is of course a SM5847 not a 4847.....
The question is that there are at least 6 formats in the I2S! From the SAA7310 the I2S is:'left justified with one bit delay' and the SM5847 needs:'right justified' (both with MSB left).
How to transform from the firts to the second format?
I thought: shift DATA 15 bits to the right, but this does not work!
You gave the suggestion: in the CD930 the WSEL and the BCLOCK are inverted and DATA is shifted 16 bits to the right.
When this should work I begin to become an old man!
I do not understand that at all.
Inverting the WSEL only exchanges left and right and what should happen with the inversion of the bit clock ???? Could be that the timing of the logic is better in this case, but in combination with shift right SIXTEEN of DATA....... ????
I like to understand what I'm doing before doing a lot of labor....
It is difficult to get where you are going if you do not know where you are. There is only one I2S format.
Dear 'rfbrw',
There is only one I2S, yes. The Philips document tells you that there are three signals: bitclock (BCL), data (DATA) and word select (WSEL). It explanes the relationship and timing on MICRO LEVEL. This document is well known to me.
READ IT YOURSELF !!!
It will tell NOTHING about the position of the DATA-word within the 32 bits of the WSEL, neither if the first bit of the DATA word is the MSB or the LSB. In other words, it does not treat the different FORMATS, which is the subject of the discussion so far.
In the mean time I have found the problem. If people are interrested I could explain it and give the solution.....
There is only one I2S, yes. The Philips document tells you that there are three signals: bitclock (BCL), data (DATA) and word select (WSEL). It explanes the relationship and timing on MICRO LEVEL. This document is well known to me.
READ IT YOURSELF !!!
It will tell NOTHING about the position of the DATA-word within the 32 bits of the WSEL, neither if the first bit of the DATA word is the MSB or the LSB. In other words, it does not treat the different FORMATS, which is the subject of the discussion so far.
In the mean time I have found the problem. If people are interrested I could explain it and give the solution.....
Well philpoole,
I discussed the whole thing with my good friend Henk ten Pierick (keep this name in mind!) and he gave me the suggestion to make a test disk with a 1 Hz, 0 dB block signal. Any audio editor can generate such signals.
Without this signal one cannot distinguish the positive from the negative data words of an I2S-signal on an oscilloscope. They will be projected on top of each other. I told before that the signals at the input of the digital filter in the CD624 (under investigation) gave the same pictures on my oscilloscope as those in a well functioning DAC with the same chip set.
In fact I generated a 1 Hz, 0 dB block in anti phase on the left and right chanel on my test disk. With this signal became immediatily clear that my 15 bit shift register (CD4006B) produced rubbish. The data was clocked on its transitions.... Inverting the bit clock before the shift.reg. gave the solution. That simple it was.....
BUT, I still do not understand what happens in the 930: inverting the bit clock and shift right 16 (sixteen!)......
I discussed the whole thing with my good friend Henk ten Pierick (keep this name in mind!) and he gave me the suggestion to make a test disk with a 1 Hz, 0 dB block signal. Any audio editor can generate such signals.
Without this signal one cannot distinguish the positive from the negative data words of an I2S-signal on an oscilloscope. They will be projected on top of each other. I told before that the signals at the input of the digital filter in the CD624 (under investigation) gave the same pictures on my oscilloscope as those in a well functioning DAC with the same chip set.
In fact I generated a 1 Hz, 0 dB block in anti phase on the left and right chanel on my test disk. With this signal became immediatily clear that my 15 bit shift register (CD4006B) produced rubbish. The data was clocked on its transitions.... Inverting the bit clock before the shift.reg. gave the solution. That simple it was.....
BUT, I still do not understand what happens in the 930: inverting the bit clock and shift right 16 (sixteen!)......
- Status
- This old topic is closed. If you want to reopen this topic, contact a moderator using the "Report Post" button.